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Proposal for a Research Grant
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"Investigations into an Environment for the
Design of Very Large Scale Integrated Circuits"


D. J. Rees
December 1981


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Introduction
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Integrated circuit fabrication technology now allows very large scale designs to
be manufactured. This is the so-called VLSI technology that has provided a
quantitative leap in complexity from LSI. Integrated circuits have recently been
announced that contain many tens of thousands of transistors and the next decade
will probably see chips with millions of transistors. This quantitative change
in complexity is of necessity bringing about a qualitative change in design
methodologies. The traditional approach to chip design has been for the designer
to hand-craft the geometry his circuit layouts using paper and pencil and to
call upon his intellectual faculties to integrate the complexities of the
overall chip. Existing computer aids have mostly been used as draughting tools
to assist this approach. With the very great increase in complexity of circuit
which can now be fabricated this approach is no longer viable. The development
of new design methodologies to overcome this problem has been led by the notions
of structured hierarchical design put forward by Mead at the California
Institute of Technology. Recent conferences including VLSI 81 which was held in
Edinburgh University have made it clear that much work still needs to be done
before full advantage can be taken of VLSI.
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A VLSI Design Environment
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The subject of this proposal is that of a VLSI design environment. By this we
mean a framework of computing facilities encompassing both hardware and software
facilities within which a designer can pursue his design developments. It should
provide a set of interrelated capabilities that can be called upon as and when
required. These need not necessarily form a tightly integrated design system as
exemplified by the GAELIC system to which the SERC provides access. At the
present state of development of design methodologies and tools, there is no
universal agreement as to what will prove to be the most fruitful lines of
development. Several parallel approaches may well be needed to cope both with a
variety of types of integrated circuit and designer preferences. It should not
be necessary and might be counter-productive to prescribe that a particular
design method should always be used. The notion of a design environment which
can accommodate these variations and which can be expanded in a variety of
different directions is therefore one which we believe should be adopted.
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The hardware of the environment needs to cope with the same variety of
approaches. Graphical input and output devices are of primary importance in
existing design methodologies and will probably remain so in the future. A
growing requirement is however for local computing power to be associated with
them in order to sustain the demands for interaction and feedback which
designers must have. Both hardcopy devices and display devices will be required.
The use of colour in information display is a further adjunct which has proved
extremely useful. Access to a powerful mainframe for computationally intense
design activities is a further requirement. Simulation systems typically require
large computational resources particularly when operating at the silicon device
level. Special-purpose hardware may be developed to assist with such activities
and it should be possible to fit this into the hardware environment.
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The software of a VLSI design environment should incorporate existing tried and
tested facilities together with more tentative and experimental facilities that
designers may like to try. The environment should also allow a designer to
develop specific tools that he may require for a particular purpose. Software
aspects are discussed further below.
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One of the keys to a successful environment is the ability to transport designs
and design fragments around the various components and subsystems. This can take
place at a number of levels. The lowest level might be the form in which final
designs are submitted for fabrication. Examples of this are Gaelic code and 
Caltech Intermediate Form (CIF). Both of these are purely geometrical
representations of the design. During the design process, the designer works at
a much higher level with functional and behavioural abstractions in addition to
geometry. This should also be capable of being captured. Designs can then be
generated which conform to these specifications either by construction or by
test and design iteration. Standard forms of description at these higher levels
will therefore play an important role within an environment.
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The existing Edinburgh VLSI design environment
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A number of VLSI design tools are already available to designers in Edinburgh
University. Many of these either originated in Edinburgh or have been
extensively developed in Edinburgh making use of experience acquired by the
substantial community of designers there.
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The Gaelic system originated from an SRC research project in the department
of Computer Science and is still available to designers in Edinburgh through
the SERC. It also forms the interface to mask-making services at the Rutherford
Laboratory. The more recently implemented tools available in Edinburgh centre
around the VAX-11/780 used by the department of Computer Science as its main
service machine for honours students and research workers. The tools make use of
both the central VAX mainframe and satellite design stations. Many of their
basic concepts have been imported from the California Institute of Technology
with which the Computer Science department has had close links over recent
years.
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The primary tool is known as "ILAP"[IL81] and consists of an extensive library of
software subroutines written in IMP which is the programming language developed
in Edinburgh primarily for systems implementation purposes but also widely used
for general purpose programming within the University [ST74]. At the lowest
level ILAP allows the designer to specify the primitive objects such as
transistors, wires and contacts that are used in the design of integrated
circuits. These primitives can be composed together to form "leaf" cells which
implement low level functions. Leaf cells can then be composed together to
form higher level objects and so on in a hierarchical fashion until the complete
chip design is specified. All this is performed by means of a program written by
the designer. This is an important concept. Programming languages provide the
very capabilities that a designer needs when he is designing a circuit. For
instance, a good design will be modular in structure. This equates with the
procedure construct of programming languages. All those design features which
form part of a module can be encapsulated in a procedural specification of it.
Another feature of chip designs is the repetition of instances of leaf cells.
The specification of this repetition naturally equates with iteration in a
programming language. Similarly, many other design requirements can be satisfied
easily within a program such as conditional assembly of cells and
parameterisation of designs.
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The ILAP framework goes much further than this, however. Higher level design
objects which find frequent application can be incorporated into the procedure
library for the benefit of all designers. The prime example of this is the
Programmable Logic Array (PLA) which often features in chip designs. One of the
ILAP procedures allows PLAs of arbitrary size and content to be generated simply
by the designer calling the procedure and giving it parameters which specify the
characteristics required and the Boolean function it is to implement. This
"soft" library can form a very useful feature of an environment and it is one
the features that we wish to develop and extend further.
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Another class of ILAP facilities consist of algorithms which a designer might
wish to make use of to solve particular design tasks. An example of these are
automatic wire-routing procedures which generate interconnection tracks between
cells. This is straightforward in concept but significant in principle in that
the wiring network generated is guaranteed to conform to a set of design rules
concerned with minimum widths and separations of design features. The notion of
"correctness by construction" is valuable and also one which we wish to pursue.
It is intended to incorporate tools into ILAP which verify cells hierarchically
as the programs run. Another example of this final class of ILAP facilities is
one which can be called upon to place input-output pads around the functional
part of a chip design. This is a very convenient ability and again can be
guaranteed to produce correct designs so reducing the load on the designer.
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The result of compiling and running an ILAP program is the generation of a CIF
description of the design. In this sense, the ILAP system can be regarded as a
"silicon compiler". In order for the designer to view what he has designed so
far, a system known as CIFSYS is available. This allows the CIF descriptions to
be displayed visually on a variety of output devices. The display devices most
used are the "Charles" colour TV displays, described below, and the colour pen
plotters. Colour has been found to be valuable when inspecting designs. Each
layer in the chip design is shown in a distinct colour and the shape overlaps
are shown as a suitable mixed shade. The pen plotters just draw outlines of
shapes rather than the solid blocks of colour displayed on the TV systems. The
combination of ILAP and CIFSYS has been used very successfully during the
1980/81 academic year. Both final year undergraduates and M.Sc. postgraduates
have undertaken VLSI design courses and used these design tools to produce over
twenty complete chip designs. The ease with which they were able to produce
quite complex designs demonstrated the effectiveness of the tools.
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The Program of Investigation Proposed
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Successful though the ILAP tools are, the environment should only be regarded as
a promising starting point from which to explore other ideas and approaches. It
is the purpose of this proposal to request support to investigate directions in
which this might be done. There are two principle directions we wish to explore.
They are:
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    1. Designer interaction with ILAP
    2. Technology-updatable design interfaces
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The present ILAP system is not interactive. Designers create their ILAP programs
with text editors and then must compile, link and run them in order to produce
the CIF description of their designs. They can then view them using the CIFSYS
system. This process takes some little time and therefore visual feedback is
rather delayed. CIFSYS also is not interactive and does not allow the designer
to alter some aspect of his design and see the effect immediately. He must go
back to his program and find the appropriate place within it to alter and hope
that this will have the desired effect. An approach which suggests much more
promise is that of an interpretive ILAP system. In such a system textual changes
to the designers ILAP program would immediately be executed. As well as
generating the CIF at this time, an equivalent of CIFSYS would also be invoked
to display the update. A system of this nature would achieve the best of both
worlds, the rapid interaction and feedback that a designer needs together
with the capabilities of a high level programming language. The precise way in
which such a system would be implemented needs to be investigated. In particular
the association of graphical display with an interpreted program can be
accomplished in a number of ways. We feel sure that a valuable system could
emerge from such an approach. Work at MIT on the Daedalus LISP-based system
[BA81] has shown promise in this direction but we strongly suspect that few
designers will wish to work in LISP and that a more conventionally based system
such as ILAP would be more attractive.
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Two aspects of structured design that have been identified from work at Caltech
are firstly leaf cell design and secondly the composition of leaf cells. ILAP is
capable of handling both but the main strength of the programming approach lies
in composition. Leaf cell design by programming directly in ILAP is somewhat
cumbersome and may still prove to be relatively so in an interpretive system.
For leaf cell design in particular an interactive graphics editor should be
valuable. Experiments have been carried out tentatively within the existing
environment and show promise. The capabilities of an interactive leaf cell
editor appear to be such that a designer's time can be very effectively
utilised. Most previous editors have been purely graphical. Whereas this is
already an improvement on the pencil and paper approach, the power of local
computation could also be harnessed towards more immediate verification of cell
designs. It should be possible to ensure that the designs created interactively
through an editor conform to the design rules in use and to have this checking
take place concurrently with the editing. Where errors creep in, they can be
visually monitored immediately. Not only can the typical dimensional checks such
as widths and separations be performed but also some electrical checks. An
interactive editor would feed back to ILAP. This could either be to the
interpretive system or to the compile and run system. This is much to be
preferred over an editor which generates low level output such as CIF. In a
sense, ILAP would be the glue which binds the editor to the environment.
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The second main direction of research is intended to be an investigation into
how changes in fabrication technology can be catered for. Even with improved
notions of hierarchical design and the use of regular structures as advocated by
Mead, a large chip can still be expected to take a considerable length of time
to design. Inevitably during this period fabrication technologies will have
improved and changed in various ways. The most obvious improvements will come in
reduced feature sizes. A circuit design based on feature sizes available at the
start of a design project will be very much out of date when the design is
complete. Not only will the chip be very much bigger but it will probably also
be slower. In a competitive environment this will not be acceptable.
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The scalable design rules introduced by Mead and Conway [ME80] for NMOS circuits
are one approach to solving the problem. Designs are based not on absolute
values of feature size dimensions but on a "lambda" unit which can be assigned
an absolute value just prior to fabrication. Over a certain range of scaling
factors this approach can be valuable but it has certain drawbacks. Firstly, the
scalable design rules are a compromise in that they were designed to be
acceptable to a wide range of fabrication lines. The result is that they are
rather conservative. Whilst it is very useful for a "silicon foundry" manager to
be able to transport the same final design around many different fabrication
lines it is not so attractive to designers who are striving for the best
possible layout for a particular process. Secondly, it is usually the case that
as a fabrication process is improved its design rules do not scale uniformly.
For instance, it may become possible to reduce the minimum feature size of, say,
the metallisation layer while that for the other layers remains the same.
The lambda scaling does not allow advantage to be taken of this.
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An alternative approach is to design at a topological level. In this case the
primitive components of a design are not represented geometrically but instead
by some abstraction. The designer places these only relative to each other upon
the various interconnect layers of the circuit. He does not specify any
dimensions or absolute positions. Design is much faster at this level of
abstraction and circuit function can be verified just as it can be at the
geometric level. Only at a late stage does the design need to be committed to
geometric values. This can be done automatically by "fleshing out" the
components and compacting them into the minimum space the design rules allow. If
the design rules have been shrunk in any respect then a smaller layout will
result. The Sticks representation introduced by Williams [WI78] has been used
for this purpose, for instance as in the "Cabbage" system of Hsueh [HS80]. The
"Gate Matrix" system of Lopez and Law [LO80] was motivated by the same
arguments. Not only does a system such as that described allow the designer to
cope with changes to the fabrication process whilst he is in the process of
designing his chip but also after the chip has been in production an improved
design can be regenerated. If a smaller chip is the result this may well be very
significant from the point of view of fabrication yield.
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Even if changes in technology are not the designers primary concern, the system
incorporates another instance of the correctness by construction philosophy. By
having the final geometry created automatically, it can again be guaranteed that
artwork conforming to the design rules will be generated. It has been suggested
that circuit designers can always produce a better layout than an automatic
system. This may be true in many instances but the advantages of the designs
being updatable and guaranteed correct should not lightly be discarded. The best
compromise might be a system that gave immediate feedback to the designer as he
proceeded at the topological level by performing compaction at frequent
intervals and displaying the result. Any tricks of the designer's trade could
then be made use of without having to rely on the automatic system to find them.
By proceeding in this manner, the compaction system need not be very
sophisticated but must be fast. Tentative experiments have been conducted on a
sticks system and the results have been sufficiently encouraging for us to wish
to pursue the idea further. INMOS Ltd. have recently been similarly encouraged
by a system of theirs. The result of such an interactive sticks system would be
the generation of ILAP programs. ILAP is again being used as the binding glue.
The natural mode of use of the system would then be as an alternative source of
leaf cell designs. This train of development can be taken a stage further in
that the cell designs can also be made to be "stretchable". This is a technique
used within the structured design methodolgy when composing leaf cells together.
Rather than interconnect cells by means of wiring tracks it is often better to
stretch one of the cells and then to abut the two cells together directly.
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Apart from these initial objectives, others may be expected to develop during
the course of the project. One such may be to build the tools around an
alternative programming language. ADA is an obvious candidate in this respect.
Such is the framework of the design environment that other directions of
research should be capable of being incorporated without difficulty. The results
of the project may well be capable of exploitation in the electronics industry.
By continuing to use VAX as a central facility, as we intend,  export of
software to industrial concerns should easily be possible since VAX machines are
rapidly becoming the de facto industry standard as vehicles for VLSI design aids.
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Staffing Requirements
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The author of this proposal is a member of the lecturing staff of the department
of Computer Science and has been heavily involved in teaching VLSI design
courses to both undergraduates and postgraduates and in the development of the
existing design environment. Previous research has centred around building
large-scale systems of which the EMAS operating system is an example [ST80].
This naturally leads forward to handling the complexities of VLSI design. Also
active in VLSI research in the department of Computer Science are J.P.Gray
(former manager of the Caltech Silicon Structures Project) and I.Buchanan
(part-time lecturers), and L.D.Smith and J.B.Tansley (lecturers). Prof.
S.Michaelson and the present author are also members of the IFIP working group
on VLSI, the latter being the British Computer Society representative. In
addition, a post is funded by SERC in support of an M.Sc. course of which VLSI
design is a main component. These individuals will be partially involved in
developments in design tools but not specifically in the developments for which
support is requested. Two new posts are requested for a period of three years to
conduct the proposed research in association with the principal investigator. By
preference they should be computer scientists with VLSI design experience. A
possible candidate for the 1A post is in mind and a graduate having recently
undertaken a VLSI design course would be suitable for the 1B post. As the main
centres of research in VLSI design are in the U.S.A. and Japan support is
requested for visits there to investigate research in progress. European work in
VLSI is accelerating and visits to various institutions in France and Germany
will also be valuable. The successor to Edinburgh's VLSI 81 is to be held in
Norway in 1983 and will again provide a forum for discussion with workers in
VLSI.
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Hardware Requirements
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An important aspect of investigating new directions in design tools is that
designers with real problems should be able to try them out to test their
effectiveness. We are fortunate in Edinburgh University in having a large
community of designers and potential designers in both the departments of
Computer Science and Electrical Engineering and the Wolfson Microelectronics
Institute. We hope that these designers would be able to use new tools as they
are produced. In order to make this possible it is our desire to make use
of the existing hardware framework and to replicate it for
the immediate use by the project staff. We believe it to be suitable for
future developments so far envisaged. One additional design station is sought
consisting of:
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     1. A "Charles" Mk.II Colour TV display system
     2. A Hewlett-Packard 7221C plotter and associated console
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The Charles colour TV display system is a development undertaken by technical
staff within the department of Computer Science of a design originating from
Caltech with VLSI specifically in mind. It is based around a Digital Equipment
Corporation LSI-11/23 processor and a frame-store having 512*512 pixels and 8
bits per pixel giving 256 mapped colours. We believe that this should give
adequate performance for the local interactive tasks that are envisaged in these
investigations. The more computationally intense requirements will still be met
by the central VAX. Possible alternative commercially available colour
terminals for VLSI design work were surveyed by "Lambda" magazine in its 2nd
quarter 1981 issue. Most did not meet the requirements as perceived but two
products, the RAMTEK 9400 and the Aydin 5216, were identified as being the best.
Both of these are significantly more expensive than the Charles display and both
lack the local processing power that an LSI-11/23 posesses. We therefore feel
that our best option is to replicate the Charles MK II design using University
facilities and technicians. The pen-plotter is an essential adjunct to the
interactive design terminal in order to get hard-copy.
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A powerful local single-user computer incorporating a colour display would be an
attractive alternative to the central VAX and the Charles terminal. Machines
such as the  Three Rivers Corporation PERQ, and a smaller personal VAX can be
expected to become available with colour display systems in the future. An
experiment to transport the Edinburgh tools onto such a design station might
form the basis of a future request for support from the SERC.
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References
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[IL81} : "ILAP Documentation", Dept. of Computer Science, 1981.

[ST74] : P.D.Stephens,"The IMP Language and Compiler",Computer Journal, Vol.17,1974.

[BA81] : J.Batali, N.Mayle, H.Shrobe, G.Sussman and D.Weise, "The DPL/Daedalus
         Design Environment", VLSI 81 Conference Proceedings, Ed. J.P.Gray, 1981,
         Academic Press.

[ME80] : C.Mead and L.Conway, Introduction to VLSI Systems", Addison-Wesley, 1979

[WI78] : J.D.Williams, "STICKS - A graphical compiler for high-level LSI design",
         AFIPS Conference Proceedings, Vol.47, 1978.

[HS80] : M.Y.Hsueh, "Symbolic Layout and Compaction of Integrated Circuits",
         Electronics Research Laboratory Memorandum no. UCB/ERL M79/80, 1979.

[LO80] : A.D.Lopez and H.F.S.Law, "A Dense Gate Matrix Method for MOS VLSI", IEEE
         Transactions on Electron Devices, Vol.27, 1980.

[ST80] : P.D.Stephens, J.K.Yarwood, D.J.Rees and N.H.Shelness, "The Evolution of the
         Operating System EMAS 2900", Software Pratice and Experience, Vol.10, 1980.
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