!!!!!!!!!!!!!!!!!!!!!!!!! ELEMENT DEFINITIONS !!!!!!!!!!!!!!!!!!!!!!!!!! %ELEMENTDEF CTR(%INPUT C1,C2,R,S,%INPUTARRAY A(0:3),%OUTPUTARRAY Y(0:3)) %ELEMENTDEF SWITCH(%INPUTARRAY A(0:7),%OUTPUTARRAY Y(0:7)) %ELEMENTDEF INV(%INPUT A,%OUTPUT Y) %ELEMENTDEF NAND2(%INPUT A,B,%OUTPUT Y) %ELEMENTDEF NAND2OC(%INPUT A,B,%OUTPUT Y) %ELEMENTDEF AND2(%INPUT A,B,%OUTPUT Y) %ELEMENTDEF BUFF(%INPUT A,%OUTPUT Y) %ELEMENTDEF NOR5(%INPUT A,B,C,D,E,%OUTPUT Y) %ELEMENTDEF NAND8(%INPUTARRAY A(0:7),%OUTPUT Y) %ELEMENTDEF MMVBR(%INPUT A1,A2,B,T9,T10,T11,%OUTPUT Q,QB) %ELEMENTDEF DFF(%INPUT C,D,P,CL,%OUTPUT Q,QB) %ELEMENTDEF MULT2(%INPUT S0,S1,A,B,%OUTPUT Y) %ELEMENTDEF MULTB2(%INPUT S0,S1,A,B,%OUTPUT Y) %ELEMENTDEF RAM8(%INPUT D,RW,CE1,CE2,CE3,%ARRAY A(0:7),%OUTPUT Y) %ELEMENTDEF RAM10(%INPUT D,RW,CE,%ARRAY A(0:9),%OUTPUT Y) %ELEMENTDEF COMP(%INPUT A,%OUTPUT Y) !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! %ASSEMBLYDEF CTR12(%INPUT C,R,S,%ARRAY A(0:11),%OUTPUTARRAY Y(0:11)) %ELEMENT(CTR) C0,C1,C2 C0.Y(0)->C0.C2 C1.Y(0)->C1.C2 C2.Y(0)->C2.C2 C->C0.C1 C0.Y(3)->C1.C1 C1.Y(3)->C2.C1 R->C0.R,C1.R,C2.R S->C0.S,C1.S,C2.S %FOR I=0,1,3 %DO [ A(I)->C0.A(I) ; A(I+4)->C1.A(I) ; A(I+8)->C2.A(I) C0.Y(I)->Y(I) ; C1.Y(I)->Y(I+4) ; C2.Y(I)->Y(I+8)] %ENDDEF !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! %ASSEMBLYDEF SELECT(%INPUTARRAY A0,A1(0:7),%OUTPUTARRAY Y(0:7)) %ELEMENT(SWITCH) S0,S1 %FOR I=0,1,7 %DO [ A0(I)->S0.A(I) ; A1(I)->S1.A(I) S0.Y(I),S1.Y(I)->Y(I) ] %ENDDEF !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! %ASSEMBLYDEF WCS7(%INPUT CMD0,DR0,DA0,SR0,ADRS0,INIT0, & %ARRAY RAH(5:15),%ARRAY IR(0:7),%OUTPUT HW0,SYN0,DISR0,DISDR1,SCLR0, & %ARRAY SRD(0:15),%ARRAY DROM(4:15),%INOUTARRAY D(0:15)) !!!!!!!!!!!!!!!!!!!!!!!!! ELEMENT DECLARATIONS !!!!!!!!!!!!!!!!!!!!!!!!! %ELEMENT(INV) ICMD,IDR,IDA,ISR,IADRS,IHW,ISYN,ISN,IAM1,IAM2,IC,IAMCL, & IWMCL,IA0,IA1,IRAH5,IDRE1,IDRE2,%ARRAY ID,IDAI2(0:15), & %ARRAY ID2(8:15),%ARRAY IDAI(0:3),%ARRAY IDDI(4:15) %ELEMENT(AND2) ACMD,ADR,ADA,ASR,ADRE,ADAE,AD,A50,A51,ADRAM %ELEMENT(NAND2) NA1,NA2,NA3,NA4,ND2,NAM,NCS,NCC,%ARRAY ND(4:15) %ELEMENT(NAND2OC)%ARRAY NDAI(0:15),%ARRAY NDDI(4:15) %ELEMENT(NOR5) NSYN %ASSEMBLY(SELECT) S %ASSEMBLY(CTR12) C %ELEMENT(NAND8) SN %ELEMENT(MULT2)%ARRAY M(4:15),%ARRAY DS(8:15) %ELEMENT(BUFF) B1,B2 %ELEMENT(COMP) RES500,RES20K,CAP10MF %ELEMENT(MMVBR) CLP %ELEMENT(DFF) AM,WM %ELEMENT(MULTB2)%ARRAY AS(4:15) %ELEMENT(RAM10)%ARRAY RAM(0:31) %ELEMENT(RAM8)%ARRAY DRAM(4:15) !!!!!!!!!!!!!!!!!!!!!!!! CMD, DR, DA, SR INPUTS !!!!!!!!!!!!!!!!!!!!!!!! CMD0->ICMD.A ICMD.Y->ACMD.A DR0->IDR.A IDR.Y->ADR.A DA0->IDA.A IDA.Y->ADA.A SR0->ISR.A ISR.Y->ASR.A !!!!!!!!!!!!!!!!!!!!!!! ADRS LATCH !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ADRS0->IADRS.A IADRS.Y->NA1.A,NA2.A NA1.Y->NA2.B,NA4.B,ISYN.A NA2.Y->NA3.A NA3.Y->NA4.A DENB1:NA4.Y DENB1->NA3.B,IHW.A,ACMD.B,ADR.B,ADA.B,ASR.B IHW.Y->HW0 !!!!!!!!!!!!!!!!!!!!!!!!! SYN OUTPUT !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ISYN.Y->NSYN.A ACMD.Y->NSYN.B ADR.Y->NSYN.C ADA.Y->NSYN.D ASR.Y->NSYN.E NSYN.Y->SYN0 !!!!!!!!!!!!!!!!!!!!!!!! DATA INPUTS & SWITCH INPUTS !!!!!!!!!!!!!!!!!!! %FOR I=0,1,15 %DO [ D(I)->ID(I).A ] %FOR I=8,1,15 %DO [ ID(I).Y->S.A1(I-8),ID2(I).A ] %FOR I=8,1,15 %DO [ ID2(I).Y->S.A0(I-8) ] !!!!!!!!!!!!!!!!!!!!!!!! DEV. NO. COMPARISON !!!!!!!!!!!!!!!!!!!!!!!!!!! %FOR I=0,1,7 %DO [ S.Y(I)->SN.A(I) ] SN.Y->ISN.A ISN.Y->NA1.B !!!!!!!!!!!!!!!!!!!!!!!!!! DR & DA ENABLE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ADR.Y->ADRE.A ADA.Y->ADAE.A WM.Q->ADRE.B,ADAE.B !!!!!!!!!!!!!!!!!!!!!!!!! DATA READ CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!! %FOR I=0,1,3 %DO [ IDAI(I).Y->D(I) ] %FOR I=4,1,14 %DO [ ND(I).Y->D(I) ] AD.Y->D(15) ND2.Y->AD.A ASR.Y->ND2.A WM.Q->ND2.B ND(15).Y->AD.B !!!!!!!!!!!!!!!!!!!!!!! READ DATA MULTIPLEXOR CONNECTIONS !!!!!!!!!!!!!! %FOR I=4,1,7 %DO [ ADRE.Y->ND(I).A ] ADRE.Y->IDRE1.A IDRE1.Y->IDRE2.A %FOR I=8,1,15 %DO [ IDRE2.Y->ND(I).A ] %FOR I=4,1,15 %DO [ M(I).Y->ND(I).B ] !!!!!!!!!!!!!!!!!!!!!!!! WRITE MODE FLIP FLOP !!!!!!!!!!!!!!!!!!!!!!!!!! ID(15).Y->WM.D ACMD.Y->WM.C INIT0->WM.P WM.Q->DISR0 %GND->IWMCL.A IWMCL.Y->WM.CL WM.QB->B1.A,B2.A B1.Y,B2.Y,RES500.Y->DISDR1 WM0:B1.Y %VCC->RES500.A !!!!!!!!!!!!!!!!!!!!!!!! CLEAR PULSE MULTIVIBRATOR !!!!!!!!!!!!!!!!!!!!! WM0->CLP.B %GND->CLP.A1,CLP.A2 CLP.Q->%N CLP.QB->SCLR0 %N->CLP.T9 RES20K.Y->CLP.T11,CAP10MF.A CAP10MF.Y->CLP.T10 %VCC->RES20K.A !!!!!!!!!!!!!!!!!!!!!!!!!!! COUNTER CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!! ACMD.Y->IAM1.A IAM1.Y->AM.P ADAE.Y->IAM2.A,NAM.A,NCS.A %GND->AM.D %GND->IAMCL.A IAMCL.Y->AM.CL AM.Q->NCS.B AM.QB->NAM.B IAM2.Y->AM.C NAM.Y->IC.A IC.Y->C.C NCS.Y->C.S NCC.Y->C.R C.Y(0)->NCC.A,IA0.A C.Y(3)->NCC.B %FOR I=0,1,11 %DO [ ID(I+4).Y->C.A(I) ] !!!!!!!!!!!!!!!!!!!!!!!! RAM ADDR MULTIPLEXOR CONNS !!!!!!!!!!!!!!!!!!!! %FOR I=5,1,15 %DO [ RAH(I)->AS(I).A ] RAH(5)->IRAH5.A IRAH5.Y->AS(4).A %FOR I=4,1,15 %DO [ WM0->AS(I).S0 %GND->AS(I).S1,M(I).S1 C.Y(0)->M(I).S0 ] IA0.Y->A51.B C.Y(1)->A51.A,IA1.A A51.Y->AS(5).B IA0.Y->A50.B IA1.Y->A50.A A50.Y->AS(4).B %FOR I=2,1,11 %DO [ C.Y(I)->AS(I+4).B ] !!!!!!!!!!!!!!!!!!!!!!!!!!!!! RAM CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!!!! %FOR I=0,1,15 %DO [ AS(4).Y->RAM(I).CE ; AS(5).Y->RAM(I+16).CE NAM.Y->RAM(I).RW,RAM(I+16).RW ID(I).Y->RAM(I).D,RAM(I+16).D ] %FOR I=0,1,9 %DO [ %FOR J=0,1,15 %DO [ AS(I+6).Y->RAM(J).A(I),RAM(J+16).A(I) ] ] !!!!!!!!!!!!!!!!!!!!!!!! RAM OUTPUT CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!! %FOR I=0,1,15 %DO [ RAM(I).Y,RAM(I+16).Y->IDAI2(I).A IDAI2(I).Y->NDAI(I).A WM0->NDAI(I).B NDAI(I).Y->SRD(I) ] %FOR I=0,1,3 %DO [ RAM(I).Y->IDAI(I).A ] %FOR I=4,1,15 %DO [ RAM(I).Y->M(I).B ] !!!!!!!!!!!!!!!!!!!!!!! DRAM ADDR MULTIPLEXOR !!!!!!!!!!!!!!!!!!!!!!!!!! %FOR I=8,1,15 %DO [ WM0->DS(I).S0 %GND->DS(I).S1 C.Y(I-4)->DS(I).B IR(I-8)->DS(I).A ] !!!!!!!!!!!!!!!!!!!!!!!! DRAM CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WM.Q->ADRAM.A IA0.Y->ADRAM.B %FOR I=4,1,15 %DO [ ADRAM.Y->DRAM(I).CE1,DRAM(I).CE2,DRAM(I).CE3 NAM.Y->DRAM(I).RW ID(I).Y->DRAM(I).D DRAM(I).Y->IDDI(I).A IDDI(I).Y->NDDI(I).A WM0->NDDI(I).B NDDI(I).Y->DROM(I) ] %FOR I=4,1,15 %DO [ DRAM(I).Y->M(I).A ] %FOR I=0,1,7 %DO [ %FOR J=4,1,15 %DO [ DS(I+8).Y->DRAM(J).A(I) ] ] %ENDDEF !!!!!!!!!!!!!!!!!!!!!!!!!! CHIP DEFINITIONS !!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!! FRIGGED ALL TO BE 16 PIN CHIPS !!!!!!!!!!!!!!!!!!!!!!! %CHIPDEF HEXINV(%ELEMENT(INV) I1,I2,I3,I4,I5,I6)=I1.A,I1.Y,I2.A,I2.Y, & I3.A,I3.Y,%GND,%N,%N,I4.Y,I4.A,I5.Y,I5.A,I6.Y,I6.A,%VCC ;! SN7404 %CHIPDEF QNAND2(%ELEMENT(NAND2) N1,N2,N3,N4)=N1.A,N1.B,N1.Y,N2.A,N2.B, & N2.Y,%GND,%N,%N,N3.Y,N3.A,N3.B,N4.Y,N4.A,N4.B,%VCC ;! SN7400 %CHIPDEF QNAND2OC(%ELEMENT(NAND2OC) N1,N2,N3,N4)=N1.Y,N1.A,N1.B,N2.Y, & N2.A,N2.B,%GND,%N,%N,N3.A,N3.B,N3.Y,N4.A,N4.B,N4.Y,%VCC ;! SN7401 %CHIPDEF QAND2(%ELEMENT(AND2) A1,A2,A3,A4)=A1.A,A1.B,A1.Y,A2.A,A2.B, & A2.Y,%GND,%N,%N,A3.Y,A3.A,A3.B,A4.Y,A4.A,A4.B,%VCC ;! SN7408 %CHIPDEF HEXBUFF(%ELEMENT(BUFF) B1,B2,B3,B4,B5,B6)=B1.A,B1.Y,B2.A,B2.Y,& B3.A,B3.Y,%GND,%N,%N,B4.Y,B4.A,B5.Y,B5.A,B6.Y,B6.A,%VCC ;! SN7407 %CHIPDEF DUALNOR5(%ELEMENT(NOR5) N1,N2)=N1.A,N1.B,N1.C,N2.A,N1.Y, & N2.Y,%GND,%N,%N,N2.B,N2.C,N2.D,N2.E,N1.D,N1.E,%VCC ;! SN74S260 ?? %CHIPDEF UNAND8(%ELEMENT(NAND8) N)=N.A(0),N.A(1),N.A(2),N.A(3),N.A(4),& N.A(5),%GND,%N,%N,N.Y,%N,%N,N.A(6),N.A(7),%N,%VCC ;! SN7430 %CHIPDEF UCTR(%ELEMENT(CTR) C)=C.S,C.Y(2),C.A(2),C.A(0),C.Y(0),C.C2,& %GND,%N,%N,C.C1,C.Y(1),C.A(1),C.A(3),C.Y(3),C.R,%VCC ;! SIG 8281 %CHIPDEF UMMVBR(%ELEMENT(MMVBR) M)=M.QB,%N,M.A1,M.A2,M.B,M.Q,%GND, & %N,%N,%N,M.T9,M.T10,M.T11,%N,%N,%VCC ;! N74121 %CHIPDEF DUALDFF(%ELEMENT(DFF) D1,D2)=D1.CL,D1.D,D1.C,D1.P,D1.Q, & D1.QB,%GND,%N,%N,D2.QB,D2.Q,D2.P,D2.C,D2.D,D2.CL,%VCC ;! N7474 %CHIPDEF QMULT2(%ELEMENT(MULT2) M0,M1,M2,M3)=M0.A,M0.B,M0.Y,M1.Y, & M1.B,M1.A,(M0.S1,M1.S1,M2.S1,M3.S1),%GND,(M0.S0,M1.S0,M2.S0,M3.S0), & M2.A,M2.B,M2.Y,M3.Y,M3.B,M3.A,%VCC ;! SIG 8233 %CHIPDEF QMULTB2(%ELEMENT(MULTB2) M0,M1,M2,M3)=M0.A,M0.B,M0.Y,M1.Y, & M1.B,M1.A,(M0.S1,M1.S1,M2.S1,M3.S1),%GND,(M0.S0,M1.S0,M2.S0,M3.S0), & M2.A,M2.B,M2.Y,M3.Y,M3.B,M3.A,%VCC ;! SIG 8266 %CHIPDEF URAM8(%ELEMENT(RAM8) R)=R.A(1),R.A(0),R.CE1,R.CE2,R.CE3, & R.Y,R.A(4),%GND,R.A(5),R.A(6),R.A(7),R.RW,R.D,R.A(3),R.A(2), & %VCC ;! SIG 82S06 %CHIPDEF URAM10(%ELEMENT(RAM10) R)=R.CE,R.A(0),R.A(1),R.A(2), & R.A(3),R.A(4),R.Y,%GND,R.A(5),R.A(6),R.A(7),R.A(8),R.A(9),R.RW, & R.D,%VCC ;! SIG 82S11 %CHIPDEF SWITCHES(%ELEMENT(SWITCH) S)=S.A(0),S.A(1),S.A(2),S.A(3), & S.A(4),S.A(5),S.A(6),S.A(7),S.Y(7),S.Y(6),S.Y(5),S.Y(4),S.Y(3), & S.Y(2),S.Y(1),S.Y(0) %CHIPDEF COMPDIL(%ELEMENT(COMP) C)=C.A,%N,%N,%N,%N,%N,%N,%N,%N,C.Y, & %N,%N,%N,%N,%N,%N !!!!!!!!!!!!!!!!!!!!!! BOARD DEFINITION & LAYOUT !!!!!!!!!!!!!!!!!!!!!!! %BOARDDEF B(%CHIPARRAY C(0:12/'ABCDEFGHJKLMN',0:8), & %EDGEARRAY CONN01,CONN02,CONN11,CONN12(0:41), & %EDGEARRAY CONN21,CONN22,CONN31,CONN32(0:24))<-%ASSEMBLY(WCS7) C(11,8)<-%CHIP(HEXINV)<-ICMD,IDR,IDA,ISR,IADRS,IHW C(12,7)<-%CHIP(HEXINV)<-ISYN,ISN,%N,%N,%N,%N C(12,6)<-%CHIP(QNAND2)<-NA1,NA2,NA3,NA4 C(11,6)<-%CHIP(QAND2)<-ACMD,ADR,ADA,ASR C(12,8)<-%CHIP(DUALNOR5)<-NSYN,%N C(10,6)<-%CHIP(QAND2)<-ADRE,ADAE,AD,%N C(8,6)<-%CHIP(HEXINV)<-ID(0),ID(1),ID(2),ID(3),ID(4),ID(5) C(8,7)<-%CHIP(HEXINV)<-ID(6),ID(7),ID(8),ID(9),ID(10),ID(11) C(8,8)<-%CHIP(HEXINV)<-ID(12),ID(13),ID(14),ID(15),%N,%N C(9,7)<-%CHIP(HEXINV)<-IDAI(0),IDAI(1),IDAI(2),IDAI(3),ID2(8),ID2(9) C(9,8)<-%CHIP(HEXINV)<-ID2(10),ID2(11),ID2(12),ID2(13),ID2(14),ID2(15) C(9,4)<-%CHIP(QNAND2)<-ND(4),ND(5),ND(6),ND(7) C(9,5)<-%CHIP(QNAND2)<-ND(8),ND(9),ND(10),ND(11) C(9,6)<-%CHIP(QNAND2)<-ND(12),ND(13),ND(14),ND(15) C(7,3)<-%CHIP(QNAND2)<-NAM,NCS,NCC,%N C(11,5)<-%CHIP(QNAND2)<-ND2,%N,%N,%N C(10,7)<-%CHIP(SWITCHES)<-S.S0 C(10,8)<-%CHIP(SWITCHES)<-S.S1 C(11,7)<-%CHIP(UNAND8)<-SN %FOR I=1,1,3 %DO [ C(8,I+2)<-%CHIP(QMULT2)<-M(4*I),M(4*I+1), & M(4*I+2),M(4*I+3) ] C(10,5)<-%CHIP(HEXINV)<-IAM1,IAM2,IAMCL,IWMCL,IDRE1,IDRE2 C(6,3)<-%CHIP(HEXINV)<-IA0,IA1,IRAH5,IC,%N,%N C(10,4)<-%CHIP(DUALDFF)<-AM,WM C(5,4)<-%CHIP(UCTR)<-C.C0 C(6,4)<-%CHIP(UCTR)<-C.C1 C(7,4)<-%CHIP(UCTR)<-C.C2 C(5,3)<-%CHIP(QAND2)<-A51,A50,ADRAM,%N C(10,3)<-%CHIP(HEXBUFF)<-B1,B2,%N,%N,%N,%N C(11,3)<-%CHIP(COMPDIL)<-RES500 C(11,4)<-%CHIP(UMMVBR)<-CLP C(12,3)<-%CHIP(COMPDIL)<-CAP10MF C(12,4)<-%CHIP(COMPDIL)<-RES20K %FOR I=1,1,3 %DO [ C(4,I+1)<-%CHIP(QMULTB2)<-AS(4*I),AS(4*I+1), & AS(4*I+2),AS(4*I+3) ] %FOR I=0,1,7 %DO [ %FOR J=0,1,3 %DO [ C(I,J+5)<-%CHIP(URAM10)<-RAM(4*I+J) ] ] C(0,4)<-%CHIP(HEXINV)<-IDAI2(0),IDAI2(1),IDAI2(2),IDAI2(3),IDAI2(4), & IDAI2(5) C(2,4)<-%CHIP(HEXINV)<-IDAI2(6),IDAI2(7),IDAI2(8),IDAI2(9),IDAI2(10), & IDAI2(11) C(3,4)<-%CHIP(HEXINV)<-IDAI2(12),IDAI2(13),IDAI2(14),IDAI2(15),%N,%N C(0,3)<-%CHIP(QNAND2OC)<-NDAI(0),NDAI(1),NDAI(2),NDAI(3) C(1,3)<-%CHIP(QNAND2OC)<-NDAI(4),NDAI(5),NDAI(6),NDAI(7) C(2,3)<-%CHIP(QNAND2OC)<-NDAI(8),NDAI(9),NDAI(10),NDAI(11) C(3,3)<-%CHIP(QNAND2OC)<-NDAI(12),NDAI(13),NDAI(14),NDAI(15) %FOR I=2,1,3 %DO [ C(4,I-2)<-%CHIP(QMULT2)<-DS(4*I),DS(4*I+1), & DS(4*I+2),DS(4*I+3) ] %FOR I=1,1,4 %DO [ %FOR J=0,1,2 %DO [ C(I+4,J)<-%CHIP(URAM8)<-DRAM(3*I+J+1) ] ] C(9,0)<-%CHIP(HEXINV)<-IDDI(4),IDDI(5),IDDI(6),IDDI(7),IDDI(8),IDDI(9) C(9,2)<-%CHIP(HEXINV)<-IDDI(10),IDDI(11),IDDI(12),IDDI(13),IDDI(14), & IDDI(15) C(10,0)<-%CHIP(QNAND2OC)<-NDDI(4),NDDI(5),NDDI(6),NDDI(7) C(10,1)<-%CHIP(QNAND2OC)<-NDDI(8),NDDI(9),NDDI(10),NDDI(11) C(10,2)<-%CHIP(QNAND2OC)<-NDDI(12),NDDI(13),NDDI(14),NDDI(15) !!!!!!!!!!!!!!!!!!!!!!!!!!! EDGE CONNECTIONS !!!!!!!!!!!!!!!!!!!!!!!!!! CONN12(20)<-CMD0 CONN11(20)<-DR0 CONN12(21)<-DA0 CONN11(19)<-SR0 CONN12(19)<-ADRS0 CONN12(26)<-HW0 CONN11(23)<-SYN0 CONN11(26)<-SCLR0 %FOR I=0,1,7 %DO [ CONN11(11+I)<-D(2*I) ; CONN12(11+I)<-D(2*I+1) ] %FOR I=0,1,7 %DO [ CONN21(24-I)<-SRD(2*I) ; CONN22(24-I)<-SRD(2*I+1) ] %FOR I=0,1,3 %DO [ CONN21(15-I)<-IR(2*I) ; CONN22(15-I)<-IR(2*I+1) ] CONN22(10)<-RAH(5) %FOR I=3,1,7 %DO [ CONN21(12-I)<-RAH(2*I) ; CONN22(12-I)<-RAH(2*I+1) ] CONN21(0)<-DISR0 %FOR I=2,1,7 %DO [ CONN31(17+I)<-DROM(2*I) ; CONN32(17+I)<-DROM(2*I+1) ] CONN31(17)<-DISDR1 CONN31(0)<-INIT0 %ENDDEF %END