DCAP : David's Circuit Assignment Program DCAP provides a method of description of circuits, the assignment of functional elements to integrated circuit chips and their layout on circuit boards. It creates data structures corresponding to the descriptions in a file which can then be used for further processing. At the present state of development of the system, this consists of producing a wire-wrap schedule for the circuit but it is also intended that it should be used for other stages in the design and construction process such as printed circuit board design, production of circuit schematics by plotter etc. Rather than use a description of the circuit in terms of functional relationships between signals, DCAP works in terms of functional elements which are regarded as 'black boxes' with inputs and outputs to be interconnected as required. In doing this, ideas familiar to users of records in IMP are used. For instance, a type of element with one input and one output (such as an inverter gate) can be described by: %ELEMENTDEF INV(%INPUT A,%OUTPUT Y) This is the equivalent of the %RECORDFORMAT statement of IMP: %RECORDFORMAT INV(%INTEGER A,%REAL Y) perhaps, which describes the format of a record of type 'INV'. Similarly, instances of the element can be declared: %ELEMENT(INV) I1,I2 which is the equivalent, in IMP, of: %RECORD I1,I2(INV) The input or output terminals of an element are represented by: I1.A I1.Y I2.A I2.Y which corresponds to IMP's: I1_A I1_Y I2_A I2_Y As already apparent, there are some differences in the syntax of DCAP as compared with IMP but this is of no real importance. DCAP uses the same form of keyword delimiting i.e. a '%' shift, and redundant spaces are ignored on input in the same way. The continuation of a statement from one line to the next is simply an ampersand character '&' instead of '%C', at the end of a line again. Statement separators are newline and semi-colon as in IMP.
Element Definitions The element definition defines the generic name of a type of element and also defines and gives names to its input and output terminals. Terminals may be of three kinds: %INPUT %OUTPUT %INOUT The %INOUT type implies that the terminal handles bidirectional i.e. both input and output signals. This is often the case for bus lines etc. Example: %INPUT A,B,C ; %OUTPUT Y,Z ; %INOUT W In addition, arrays of terminals can be described: %INPUTARRAY X(1:8) %OUTPUTARRAY U,V(9:15) Bounds of arrays must be positive constants or zero. The number of terminals an element may have is not limited. Names here, as throughout DCAP, consists of up to eight letters or digits starting with a letter. A gate such as: might be described as: %ELEMENTDEF NAND(%INPUT A,B,%OUTPUT Y) and a register such as: data in ock clear data out might be described as: %ELEMENTDEF HEXREG(%INPUT CLEAR,CLOCK,%INPUTARRAY DI(1:6), & %OUTPUTARRAY DO(1:6)) Discrete components such as resistors, capacitors and transistors etc. can also be described in this way. %INOUT terminals are often convenient in these cases as the concept of the direction of a signal
may be superfluous. DCAP defines: %ARRAY <name list> ( <bounds> ) as a unit of syntax implying an array of the same input-output type as the preceding part of the statement. For example: (%INPUT A,B,%ARRAY C(1:2),%ARRAY D(3:4)) is equivalent to: (%INPUT A,B,%INPUTARRAY C(1:2),%INPUTARRAY D(3:4)) The form of syntax in IMP array declarations: ....%ARRAY E(5:6),F(7:8) is not permissible. Element Declaration Instances of single elements or arrays of elements are declared by statements of the form: %ELEMENT(NAND) N %ELEMENT(HEXREG)%ARRAY REG(0:3) %ELEMENT(INV) I,J,K,%ARRAY L(1:6) The generic type, in brackets, must have been previously defined. The keyword '%ELEMENT' can be elided as the last example shows to allow declaration of single elements and arrays of elements of the same type in the same statement. Elements of different types have to be declared in separate statements. Array bounds should again be non-negative. Connection of Terminals The basic form of the statement which specifies a connection is: terminal -> terminal For instance: I.Y -> N.A which denotes a connection between the 'Y' output of the inverter element 'I' and the 'A' input of the NAND gate 'N'. A circuit such as:
could be described by: %ELEMENT(NAND) FF1,FF2 FF1.Y -> FF2.A FF2.Y ->FF1.B The remaining terminals would be connected to other elements in a similar way. The basic statement can be generalised in two ways. Firstly, if a signal is distributed from one output to several other inputs, these inputs can be listed on the right-hand-side of the '->'. For example: I.Y -> N1.A , N2.A , N3.A Secondly, there can be a list of outputs on the left-hand-side of the '->' to allow for the connections together of several outputs as occurs with open-collector devices, for instance: N1.Y , N2.Y , N3.Y -> I.A The two forms of extension can be combined in one statement. Power and ground connections can be made by specifying the keywords %VCC and %GND respectively in place of terminal names: %VCC->N1.B ; N2.Y->%GND %VCC and %GND can appear on either side of the '->'. (Note that whereas %GND can perhaps be used as a 'low' logic level, %VCC is not a 'high' logic level. %VCC denotes the supply voltage i.e. 5V for TTL.) These need only be used for exceptional cases, however, as the power and ground connections to integrated circuit chips are specified elsewhere. The direction of the signal must be correctly specified. The left-hand-side should be the source of the signal i.e. normally an %OUTPUT from an element (though see Assembly definitions below) and the right-hand-side the destination i.e. normally an %INPUT. DCAP checks this as an aid to debugging the specification of the circuit. Naming Signals On a circuit diagram, some of the signals are usually named to aid in its comprehensibility. The DCAP notation of 'element name.terminal name' is often not mnemonic for a signal and so a facility is provided. The statement which does the naming takes the form:
signal name : element terminal name For example: ENABLE0 : N3.Y Thereafter, the name 'ENABLE0' can be used inplace of 'N3.Y' in any connection statement. Both input and output terminals can be named in this way. Loop Statements One of the most powerful features of DCAP is the ability to declare arrays of terminals and elements and then to index them within loops. In other words, given the array declaration: %ELEMENT(NAND)%ARRAY M,N(1:4) the statements: %ELEMENT(NAND)%ARRAY M,N(1:4) M(1).Y -> N(1).A M(2).Y -> N(2).A M(3).Y -> N(3).A M(4).Y -> N(4).A can be written using a loop statement: %FOR I=1,1,4 %DO [ M(I).Y -> N(I).A ] The interpretation of this is that the statement, or statements (in general), inside the square brackets are repeated with the index variable 'I' taking a different value each time: 1, 2, 3 & 4. These values are spcified by the '1,1,4' part of the statement which means that the first value is 1, the increment to this value for each repetition is 1 and the final value is 4. I.e.: first,increment,final The three quantities can have any values (including negative), but the increment must not be zero and the following relationship must hold: final - first ------------- = a non-negative integer increment This just states that in adding the increment to the first value successively, the index will eventually exactly equal the final value. Index variable names can be invented and used without declaration as they would have to be in a language such as IMP. Any number of statements can be contained within the square brackets separated by newline or semi-colon in the ordinary way:
%FOR . . . . %DO [ ... ; ... ; ... ... ; ... ; ... ] Also, further loop statements can be nested within the square brackets. This may be done to a nesting depth of eight (an arbitrary limit, however, which could be increased). Expressions The loop index values (first, increment and final) and any array index can, in general, be expressions. These involve index variables and constants combined with the usual operators: + - * / with the normal interpretation, '/' giving an 'integer' division i.e. an integer result. For example: %ELEMENT(NAND)%ARRAY P(1:4),%ARRAY Q(1:16) %FOR I=0,1,3 %DO [ %FOR J=0,1,3 %DO [ P(I+1).Y -> Q(4*I+J).A ] ] Assembly Definitions It is often found within a circuit that some particular sub-circuit recurs in several places. In order to avoid repetitive specifications of such sub-circuits, DCAP allows them to be defined as 'assemblies'. The definition of the assembly is given once and then instances of the assembly can be declared just as instances of elements are declared. An assembly will consist of a number of internal elements together with their connections and also external inputs and outputs. In this latter respect they are again similar to elements and in a like manner their inputs and outputs can be connected up to the rest of the circuit. The first statement of the definition takes the form, for example: %ASSEMBLYDEF COUNTER(%INPUT CLOCK,%OUTPUTARRAY COUNT(1:12) This specifies the assembly's inputs and outputs and it must immediately be followed by the specification of the assembly's internals. The definition is terminated by the statement: %ENDDEF As an example, if a D-type flip-flop was to be built up from NAND gates using the circuit:
preset clear Q _ clock Q D the following would specify it: %ELEMENTDEF NAND3(%INPUT A,B,C,%OUTPUT Y) %ASSEMBLYDEF DTYPEFF(%INPUT PRESET,CLEAR,CLOCK,D,%OUTPUT Q,QB) %ELEMENT(NAND3) N1,N2,N3,N4,N5,N6 PRESET -> N1.A,N5.A CLEAR -> N2.B,N4.B,N6.B CLOCK -> N2.C,N3.B D -> N4.C N1.Y -> N2.A N2.Y -> N1.C,N3.A,N5.B N3.Y -> N4.A,N6.C N4.Y -> N1.B,N3.C N5.Y -> Q,N6.A N6.Y -> QB,N5.C %ENDDEF Note that the assembly input-output terminals are connected internally to give a complete specification. (The source of an external signal is an %INPUT terminal and goes on the left-hand-side. Similarly an external destination is an %OUTPUT terminal and appears on the right-hand-side.) Note also that the definitions of any elements declared within an assembly must have preceded the assembly definition. In the particular example above, it would not, perhaps, be normal to build it from discrete NAND gates but to use an IC for the purpose. Then it would, of course, have been defined as an element. Assembly Declarations The form of assembly declaration is the same as that for element declaration just with the different keyword. For example: %ASSEMBLY(DTYPEFF) D,%ARRAY E,F(1:4) Assemblies can be declared within other assemblies and any number of 'layers' of nesting are permitted i.e. assembloes within assemblies within assemblies etc. The only restrictions are that an assembly cannot be declared recursively i.e. within its own definition and that assembly definitions cannot be nested.
Assembly terminals are thereafter used exactly as element terminals are, for example: D.Q -> E(1).D Assignment of Circuits to Hardware What has been described above is purely concerned with the logic of a circuit. DCAP goes a stage further and provides a method of describing the translation of such a circuit into hardware, in particular the assignment of logic elements to integrated circuit chips, the assignment of chips to positions on a circuit board and the specification of board edge connections. In order to be able to do the first of these three things, types of chips have to be defined. To do the other two things, the geometry of the particular circuit board has to be described. DCAP has a facility which allows all three things to be done in quite a general manner that can be applied to any kinds of chip and board. The circuit to be assigned to a board is defined as a single assembly definition. If the circuit is essentially two or more separate assemblies, they must be declared as instances of their definition inside a single further assembly definition. The inputs and outputs of this single assembly definition form the inputs and outputs of the board i.e. the signals at the edge connecters. Chip Definitions An integrated circuit chip may hold one or more logic elements e.g. a 'hex inverter' chip holds six inverter gates. The chip definition reflects this in that the chip definition contains a declaration of what elements are implemented on the chip. It then defines what each pin of the chip is. The definition consists of one statement only. The first part of it defines the elements. For example: %CHIPDEF HEXINV(%ELEMENT(INV) I1,I2,I3,I4,I5,I6) . . . . Assuming that a definition for the name 'INV' has appeared previously, this indicates that a chip of type 'HEXINV' is being defined which holds six elements of type 'INV' named I1,I2, etc. These names are used to specify the pins of the chip in the remainder of the statement and have no other purpose. The pin definitions take the form of a list of terminal names. To continue the above example: =I1.A,I1.Y,I2.A,I2.Y,I3.A,I3.Y,%GND,I4.Y,I4.A,I5.Y,I5.A,I6.Y,I6.A,%VCC Thus 'I1.A' relates to pin 1, 'I1.Y' relates to pin 2 and so on in order along the list. Hence the first inverter on the chip has its 'A' input on pin 1 and its 'Y' output on pin 2. Similarly for the other elements. The symbols %GND and %VCC indicate the ground and power pins respectively. Unassigned pins i.e. those pins not connected to anything within the chip, must be indicated by the symbol '%N'.
Although perhaps unusual, elements of different types can appear in the definition, as also can arrays of elemets. A complete example of a chip definition might be: %CHIPDEF TI74174(%ELEMENT(HEXREG) R)= & R.CLEAR,R.Q(1),R.D(1),R.D(2),R.Q(2),R.D(3),R.Q(3),%GND, & R.CLOCK,R.Q(4),R.D(4),R.Q(5),R.D(5),R.D(6),R.Q(6),%VCC Alternatively, this chip could have been regarded as an array of six separate D-type flip-flop elements with common clock and clear inputs. As will be seen below, this would allow individual D-type flip-flop elements to be used in the assembly definition rather than 6-bit register elements. This could have been specified as: %CHIPDEF TI74174(%ELEMENT(DTYPEFF)%ARRAY F(1:6))= & (F(1).CLEAR,F(2).CLEAR,F(3).CLEAR,F(4).CLEAR,F(5).CLEAR,F(6).CLEAR), & F(1).Q,F(1).D,F(2).D,F(2).Q,F(3).D,F(3).Q,%GND, & (F(1).CLOCK,F(2).CLOCK,F(3).CLOCK,F(4).CLOCK,F(5).CLOCK,F(6).CLOCK), & F(4).Q,F(4).D,F(5).Q,F(5).D,F(6).D,F(6).Q,%VCC Enclosing the list of common terminals in brackets has the effect of assigning them all to the same pin. Instances of chips are declared as part of the chip assignment statement within a board definition. Board Definitions The heading statement of a board definition specifies the physical structure of the board in terms of positions available for IC chips and the edge connecters on the board. It also specifies the assembly defined to be laid out on the board. Then follow the statements which specify the assignments of logic elements to chips and chips to board positions and the assignment of assembly input-output terminals to edge connecter positions. Finally, the statement: %ENDDEF terminates the definition. At this point, DCAP produces the wire-wrap schedule for the board. (See also the 'DISTANCE' function section). The format of the heading statement is: %BOARDDEF board name( . . . . .) <= %ASSEMBLY(assembly def name) Inside the brackets is a list of declaration-like clauses for the chip positions and edges. For example: %CHIPARRAY IC(1:3,1:8) specifies an array of 24 chip positions named 'IC' in a 3*8 grid. All chip positions must be specified as two-dimensional arrays in this way. The array bounds can be any non-negative constants. Edge connecters are similarly specified, but as one-dimensional arrays. For example:
%EDGEARRAY A(1:18) As before, the keywords %CHIP and %EDGE can be elided to avoid repetition. A complete heading statement might be: %BOARDDEF BD(%CHIPARRAY IC(1:3,1:8),%EDGEARRAY A1,A2(1:18)) & <- %ASSEMBLY(AD) DCAP insists that chip and edge arrays should have numerical bounds in order to allow them to be indexed in loops (see below). However, very often in practice either the rows or the columns of chip positions and the edge connecters are lettered rather than numbered. DCAP has a facility which allows this also. Following the bounds, the letters for all the positions are written as these examples show: %CHIPARRAY IC(1:3/'ABC',1:8) %EDGEARRAY A1(1:18/'ABCDEFHJKLMNPRSTUV') Thereby, the positions can be referenced either numerically or symbolically using the letter enclosed in quotes: IC('A',2) A1('T') Quoted letters may not appear in expressions. The information in the wire-wrap schedules uses symbolic references where these are provided. A board may have any number of separate chip arrays and edge arrays. More than one chip array is often necessary when the board is designed for packages of various sizes, for example some 24 pin or 40 pin sockets in addition to 14 or 16 pin sockets. Component positions for resistors and capacitors etc. are defined using chip array declarations for 2-pin chips. Chip Assignment The general form of statement is: chip position <- chip instance <- list of elements For example: IC('A',2) <- %CHIP(HEXINV) <- L(1),L(2),L(3),L(4),L(5),L(6) allocates the six inverter elements L(1) to L(6) to a chip of type 'HEXINV' and assigns this to position IC('A',2) on the board. The order in which the elements appear in the list corresponds to the order in which the elements were declared in the chip definition of the type specified in %CHIP(...). There must be as many elements in the list as elements in the chip definition. For any element on the chip not used, '%N' must be inserted in the list. In the example above, it was assumed that the elements L(1) to L(6) were declared as an array in the assembly definition whose name is
specified at the end of the board definition header statement, '%ASSEMBLY(...)'. It is also necessary to allocate elements declared within sub-assemblies to chips. In this case, the name of the element alone may be ambiguous (when two instances of the same type of assembly are declared). The name of the element can be specified completely, however, by preceding the element name with the name of the assembly in which it appears and the symbol '.'. For example, suppose two 'DTYPEFF' assemblies (of NAND gates) were declared within the assembly to be laid out on the board: %ASSEMBLY(DTYPEFF) P,Q Then the element names to be used in the list would be: P.N1,P.N2,...Q.N1,Q.N2... etc. For further levels of nesting of assemblies, all the names of the nested assemblies appear, for example: A1.A2.A3.A4.EL when 'EL' is declared within 'A4' which is declared within 'A3' etc. This type of statement may appear within loops. For example: %FOR I=1,1,3 %DO [ IC(I,8) <- %CHIP(TI74174) <- REG(I) ] Edge Connection Assignment The form of this statement is: edge connecter position <- assembly def input-output terminal For example: A1('T') <- D Each input-output terminal of the assembly laid out on the board (and only those) must be assigned to an edge connecter position in this way. This statement can also appear in loops. For example: %FOR I=1,1,4 %DO [ A1(I+2) <- BUS(9-I) ] The Wire-wrap Facility Upon reaching the %ENDDEF statement of a board definition the present version of DCAP (DCAP version A) produces wire-wrap information to facilitate the production of the board. It does this in two forms, firstly, a listing which can be used for manual wire-wrapping and secondly, a file which when output to paper tape will drive the ERCC
WWM-600 semi-automatic wire-wrapping machine. In order to produce the positioning information the wire-wrapping machine requires, the positions of the wire-wrap posts on the board must be supplied to DCAP. This is done by means of an '%EXTERNALROUTINE' named 'POSITION' which must be provided by the user. (A library of such routines for the boards in common use is, however, being built up.) DCAP calls the 'POSITION' routine (linked dynamically on EMAS) for each pin in the connection nets. For wire-wrap schedules to be useful, the terminals in each connection net must be sensibly ordered. The most obvious aim is to order the terminals in such a way that the minimum total interconnection wire-length results. This is the well-known 'Travelling Salesman' problem. DCAP contains a simple algorithm which nevertheless performs adequately well on this task. Clearly, the distance between any two pins must be available to DCAP. For most boards, an as-the-crow-flies route between pins is possible and in this case DCAP could calculate the distance from the pin position information. Unfortunately, for some boards, the top-wrap Interdata board being an example, such a route is not in general possible. DCAP therefore requires the user also to provide an '%EXTERNALREALFN' named 'DISTANCE' to calculate the distance. The specification of the 'POSITION' routine is, in IMP terms: %EXTERNALROUTINESPEC POSITION(%STRING(8) NAM,%INTEGER ROW,COL, %C PIN,NOP,%REALNAME X,Y) The parameters relate to the information given in the board definition. For example, if there was a chip array in the definition: %CHIPARRAY IC(1:3,1:8) and the position of pin 14 of the chip in position IC(1,4) was required, the routine would be called with the parameter 'NAM' having the value 'IC', 'ROW' having the value 1 (numerical values are always used, not symbolic ones), 'COL' the value 4 and 'PIN' the value 14. The parameter 'NOP' contains the number of pins the chip assigned to that chip array position has. This information is necessary where, for example, a mixture of 14 and 16 pin chips are being used in one chip array. For instance, pin 14 will clearly be in differing positions on a 14 pin chip and on a 16 pin chip. The routine is expected to return the coordinates of the calculated position in the variables X and Y. For the purposes of the wire-wrap machine, the origin can be regarded as the left-hand bottom corner of the board when mounted in the machine with the write-wrap posts facing out towards the operator. The units of measurement of X and Y must be inches and of an accuracy precise enough for the indicating arm of the machine to move to an unambiguous position. The machine works in 1/200 inch increments in both X and Y directions. The specification of the 'DISTANCE' function is: %EXTERNALREALFNSPEC DISTANCE(%STRING(8) NAM1,%INTEGER ROW1,COL1, %C PIN1,NOP1,%REAL X1,Y1,%STRING(8) NAM2,%INTEGER ROW2,COL2,PIN2, %C NOP2,%REAL X2,Y2) The two sets of parameters have the same significance as above, one set for each pin. It will be noted that the X and Y parameters are
value-type. In other words, the position information already supplied to DCAP by the 'POSITION' routine is passed back to the 'DISTANCE' function to avoid the 'POSITION' routine most probably having to be called twice again. For an as-the-crow-flies route, this function will be almost trivial, the result required being: SQRT((X1-X2)**2+(Y1-Y2)**2) Wire-wrap Schedule Listings Several different tables of information are produced. Firstly, an ordered list of the types of chip to be mounted on the board and then lists of power and ground connections. These latter are listed separately from the main wiring connections as power and ground planes are commonly bussed around a board to be conveniently accessible from each chip position. The main wiring connections are listed in groups comprising those terminals in the same net. The order in which they are given produces a scheme of the form: which minimises the number of wires that have to be moved when making circuit alterations. Each connection listed has an indication of whether the wire is a bottom wrap (B) or a top wrap (T). This provides an on-going check during the wiring process. The length of each wire is also printed out. The next information printed out is a count of the number of wires of each different length required. This can be used when buying-in precut and stripped wire or prepreparing wire lengths. After this are a sequence of check lists for each chip and edge which give the number of wraps there should be on each pin when the wiring has been completed. This is a particularly useful checking aid. Finally, there are three cross-reference lists between names of terminals, pin positions and nets. These are intended to aid debugging and testing the board. A complete example of the output appears at the end of this document. Comments Comments can be interspersed among DCAP input statements to aid legibility and documentation. They are written as separate statements the first character of which is '!'. For example: ! THIS IS A COMMENT ENABLE0 -> N1.A,N2.A ;! SO IS THIS
%END Statement Any number of assembly definitions and board definitions may appear in one DCAP input file. The final statement of the file must be: %END Using DCAP The object file comprising the DCAP program is 'ECSC04.DCAPA'. It is called with the command 'DCAPA' and takes four parameters: DCAPA(source file, listing file, data structure file, paper tape file) If any of the parameters are omitted the defaults are: source : .TT listing : DCAPLIST data structure : DCAPFILE paper tape : DCAPTAPE Example of a complete circuit and layout A 2-bit demultiplexer built from NAND gates and inverters: 0 A0 1 A1 2 _ E 3 which is to be laid out on a (DEC-like) board of the form:
The following is a DCAP description for this example: %ELEMENTDEF INV(%INPUT A,%OUTPUT Y) %ELEMENTDEF NAND3(%INPUT A,B,C,%OUTPUT Y) %ASSEMBLYDEF DEMULT2(%INPUT A0,A1,E,%OUTPUTARRAY D(0:3)) %ELEMENT(INV) I01,I02,I11,I12,IE %ELEMENT(NAND3)%ARRAY N(0:3) A0->I01.A I01.Y->I02.A,N(0).A,N(2).A I02.Y->N(1).B,N(3).A A1->I11.A I11.Y->I12.A,N(0).B,N(1).A I12.Y->N(2).B,N(3).B E->IE.A %FOR I=0,1,3 %DO [ IE.Y->N(I).C ; N(I).Y->D(I) ] %ENDDEF %CHIPDEF HEXINV(%ELEMENT(INV) I1,I2,I3,I4,I5,I6)=I1.A,I1.Y,I2.A,I2.Y, & I3.A,I3.Y,%GND,I4.Y,I4.A,I5.Y,I5.A,I6.Y,I6.A,%VCC %CHIPDEF TRIPLEN3(%ELEMENT(NAND3) N1,N2,N3)=N1.A,N1.B,N2.A,N2.B,N2.C, & N2.Y,%GND,N3.Y,N3.A,N3.B,N3.C,N1.Y,N1.C,%VCC %BOARDDEF DEC(%CHIPARRAY IC(1:3/'ABC',1:2),%EDGEARRAY A(1:18/ & 'ABCDEFHJKLMNPRSTUV'))<-%ASSEMBLY(DEMULT2) IC('A',1)<-%CHIP(HEXINV)<-I01,I02,I11,I12,IE,%N %FOR I=0,1,1 %DO [ IC('B',I+1)<-%CHIP(TRIPLEN3)<-N(2*I),N(2*I+1),%N ] A(5)<-A0 A(6)<-A1 A(7)<-E %FOR I=0,1,3 %DO [ A(I+8)<-D(I) ] %ENDDEF %END Suitable 'POSITION' and 'DISTANCE' routines for this board might be: