! A test program testing all the modules of ILAP %include "ilap.inc" %external %routine %spec RAM %alias "ILAP_RAM" (%integer X, Y) %begin %routine start test (%string (63) name) %integer I newline print symbol ('#') %for I = 1, 1, 72 newline newline print string (name) newline newline %end INITIALISE ("TESTALL") !############################################################################### !# # !# T E S T 1 : A test of the ILAP contact symbols # !# # !############################################################################### %begin start test ("The ILAP Contact symbols") symbol ("contacts") pdbns (10, 10) pdbew (20, 10) pdbn (0, 20) pdbs (10, 20) pdbe (20, 20) pdbw (30, 20) pdcn (0, 30) pdcs (10, 30) pdce (20, 30) pdcw (30, 30) pdmn (0, 0) pdms (10, 0) pdme (20, 0) pdmw (30, 0) pm (10, 40) dm (20, 40) end symbol %end !############################################################################### !# # !# T E S T 2 : A test of all the types of ILAP transistor # !# # !############################################################################### %begin start test ("The ILAP transistors") symbol ("transistors") DTDBX ("Dep Tran Diff Bur X", 8, 8, 16) DTDX ("Dep Tran Diff X", 4, 18, 9) DTDY ("Dep Tran Diff Y", 26, 18, 2) DTPX ("Dep Tran Poly X", 4, 28, 9) DTPY ("Dep Tran Poly Y", 26, 28, 2) ETDX ("Enh Tran Poly X", 4, 38, 9) ETDY ("Enh Tran Poly Y", 26, 38, 2) ETPX ("Enh Tran Poly X", 4, 48, 9) ETPY ("Enh Tran Poly Y", 26, 48, 2) end symbol %end !############################################################################### !# # !# T E S T 3 : A shift register + test of the DRC # !# # !############################################################################### %begin %routine %spec make shift register (%integer number of cells) start test ("A sample ILAP program with design rule checking") DRC ON SYMBOL ("inverter") ETPX ("ET", 2, 5, 6) { Enhancement transistor at (2,5) of length 6 } DTDBY ("DT", 4, 11, 7) { Depletion transistor including contact } DM (5, 2) { Diffusion to Metal contact for GND } DM (5, 21) { Diffusion to Metal contact for VDD } LAYER (METAL); WIDTH (4) GND WIRE X (0, 0, 10) VDD WIRE X (0, 19, 10) LAYER (DIFFUSION) WIREX (6, 8, 4) { Output line } END SYMBOL SYMBOL ("pass transistor") ETDX ("PT", 2, 8, 2) { The pass transistor } LAYER (METAL); WIDTH (4) GND WIRE X (0, 0, 6) VDD WIRE X (0, 19, 6) LAYER (POLY) WIREY (2, 0, 26) { Clock line } END SYMBOL SYMBOL ("interface cell") PDBW (3, 9) { Change from diffusion to poly for next stage } LAYER (POLY) WIREX (2, 5, 4) LAYER (METAL); WIDTH (4) GND WIRE X (0, 0, 6) VDD WIRE X (0, 19, 6) END SYMBOL SYMBOL ("shift cell") DRAW ("inverter", 0, 0) DRAW ("pass transistor", SX ("inverter"), 0) DRAW ("interface cell", SX ("inverter") + SX ("pass transistor"), 0) END SYMBOL make shift register (4) DRC OFF %routine make shift register (%integer number) %integer loop count SYMBOL ("shift register") %for loop count = 1, 1, number %cycle DRAW ("shift cell", SX ("shift cell") * (loop count - 1), 0) %repeat END SYMBOL %end %end !############################################################################### !# # !# T E S T 4 : A test of the PLA generators # !# # !############################################################################### %begin %integer a, b %integer %array in, out (1:5) %own %integer %array is (1:3) = bottom, top, bottom %own %integer %array os (1:5) = bottom, top, top, bottom, bottom %integer %array null (1:1) start test ("A test of the PLA generators") tpla ("Pla Normal", "pla", a, b, in, out) stpla ("Pla Top Out", "pla", top outputs, null, null, a, b, in, out) stpla ("Pla Top In", "pla", top inputs, null, null, a, b, in, out) { Set up positions for inputs and outputs } in (a) = 35 + (a-1)*20 %for a = 1, 1, 3 out (a) = 150 + (a-1)*20 %for a = 1, 1, 5 ! sepla ("Pla Stretch", "pla", stretch, null, null, a, b, in, out) ! sepla ("Pla Mixed", "pla", mixed inputs+mixed outputs+stretch, ! is, os, a, b, in, out) %end !############################################################################### !# # !# T E S T 5 : A test of the ROM generator # !# # !############################################################################### %begin %integer a, b %integer %array in, out (1:50) start test ("A test of the ROM generator") rom ("rom", "rom", a, b, in, out) %end !############################################################################### !# # !# T E S T 6 : A test if the Stack generator # !# # !############################################################################### %begin %routine do stack (%integer b, w, %string (31) s) %integer stx, sty, cox, coy, pux, pox, p1y, p2y, p3y, p4y %integerarray puy, poy (1:b) %integer i stack(s, b, w, cox, coy, pux, pox, p1y, p2y, p3y, p4y, puy, poy) %end start test ("A test of the Stack generator") do stack (1, 1, "S11") do stack (1, 2, "S12") do stack (1, 3, "S13") do stack (2, 4, "S24") do stack (4, 2, "S42") %end !############################################################################### !# # !# T E S T 7 : A test if the Counter generator # !# # !############################################################################### %begin %integer suby, loady, vddy, phi2y, phi1y, gndy, i %const %integer max n = 16 %integer %array ins, outs, outsb (1:max n) start test ("A test of the Counter generator") counter ("counter 3", 3, suby, loady, vddy, phi1y, phi2y, gndy, ins, outs, outsb) print string (" Sub Y = "); write (suby, 3); spaces (3) print string (" Load Y = "); write (loady, 3); spaces (3) print string (" VDD Y = "); write (vddy, 3); newline print string (" Gnd Y = "); write (gndy, 3); spaces (3) print string (" Phi1 Y = "); write (phi1y, 3); spaces (3) print string (" Phi2 Y = "); write (phi2y, 3); newline print string (" IN s : ") write (ins(i), 4) %for I = 1, 1, 3 newline print string (" Outs : ") write (outs(i), 4) %for I = 1, 1, 3 newline print string (" Outsb : ") write (outsb(i), 4) %for I = 1, 1, 3 newline counter ("counter 4", 4, suby, loady, vddy, phi1y, phi2y, gndy, ins, outs, outsb) %end !############################################################################### !# # !# T E S T 8 : A test of the RAM generator # !# # !############################################################################### %begin %integer X, Y %integer %array in, out (1:50) start test ("A test of the RAM generator") ram (6, 3) %end !############################################################################### !# # !# T E S T 9 : A test of the ILAP river-router # !# # !############################################################################### %begin %record (port) %array a, b (1:12) %constinteger mwid=3 ;! metal line width %constinteger msep=3 ;! metal line separation %integer i,sepn start test ("A test of the river-router") %for i=1,1,12 %cycle a(i)_x = 7*i+35 a(i)_w = 4 b(i)_x = 15*(i-1) b(i)_w = 4 %repeat sepn = route ("river route", a, b, 12, metal, mwid, msep, 0) symbol("river route demo") pm (a(i)_x+2, 1) %for i=1,1,12 draw ("river route", 0, 0) dm (b(i)_x+2, sepn-1) %for i=1,1,12 endsymbol %end !############################################################################### !# # !# T E S T 10 : A test of the ILAP corner router # !# # !############################################################################### %begin %record (port) %array a, b (1:6) %constant %integer mwid = 3 {metal width} %constant %integer msep = 3 {metal separation} %integer i, ya, xb start test ("A test of the corner-router") ya = 0 xb = 100 %for i = 1, 1, 6 %cycle a(i)_x = xb - 15*i a(i)_w = 4 b(i)_x = ya + 12*i b(i)_w = 4 %repeat croute("corner route", a, b, 6, ya, xb, metal, mwid, msep) symbol("corner route demo") pm(a(i)_x+2, ya+1) %for i = 1, 1, 6 draw("corner route", 0, 0) dm(xb-1, b(i)_x+2) %for i = 1, 1, 6 endsymbol %end !############################################################################### !# # !# T E S T 11 : A test of the ILAP side router # !# # !############################################################################### %begin %constinteger ac=6,ab=3,bc=4,cd=2,da=4 %constinteger ya=0,xb=120,yc=80,xd=0 %record(port)%array a(1:da+ac+ab),b(1:ab+bc),c(1:cd+ac+bc),d(1:da+cd) %integer i,j,k,l start test ("A test of the side-router") a(i)_x = 8*i %and a(i)_w = 4 %for i = 1, 1, da+ac+ab b(i)_x = 7*i %and b(i)_w = 3 %for i = 1, 1, ab+bc c(i)_x = 8*i %and c(i)_w = 3 %for i = 1, 1, cd+ac+bc d(i)_x = 12*i %and d(i)_w = 4 %for i = 1, 1, da+cd sroute ("side route",a,b,c,d,ac,ab,bc,cd,da,ya,xb,yc,xd,metal,3,3) symbol("side route demo") draw("side route", 0, 0) pm(a(i)_x+2, ya+1) %for i = 1, 1, da+ac+ab dm(xb-1, b(i)_x+1) %for i = 1, 1, ab+bc pm(c(i)_x+1, yc-1) %for i = 1, 1, cd+ac+bc dm(xd+1, d(i)_x+2) %for i = 1, 1, da+cd endsymbol %end !############################################################################### !# # !# T E S T 12 : A test of the ILAP channel router # !# # !############################################################################### %begin %routine test channel ! makes a test channel ! %record (channel port) %name port ! %string (15) name ! ! ! inits ! port == nil ! name = "Test Channel" ! ! ! net 24 ! port == declare port(name, left, 10, poly, left, 200, poly, port) ! port == declare port(name, left, 10, poly, left, 310, poly, port) ! ! ! net 9 ! port == declare port(name, left, 20, poly, right, 60, poly, port) ! port == declare port(name, left, 20, poly, right, 220, poly, port) ! port == declare port(name, left, 20, poly, right, 330, poly, port) ! port == declare port(name, left, 20, poly, left, 380, diffusion, port) ! ! ! net 1 ! port == declare port(name, left, 30, poly, right, 120, poly, port) ! port == declare port(name, left, 30, poly, left, 150, poly, port) ! port == declare port(name, left, 30, poly, left, 190, poly, port) ! port == declare port(name, left, 30, poly, left, 220, poly, port) ! ! ! net 3 ! port == declare port(name, left, 40, poly, left, 60, poly, port) ! port == declare port(name, left, 40, poly, left, 90, poly, port) ! port == declare port(name, left, 40, poly, right, 110, poly, port) ! port == declare port(name, left, 40, poly, left, 120, poly, port) ! ! ! net 14 ! port == declare port(name, left, 50, poly, right, 10, poly, port) ! ! ! net 2 ! port == declare port(name, left, 70, poly, left, 100, poly, port) ! port == declare port(name, left, 70, poly, left, 170, poly, port) ! port == declare port(name, left, 70, poly, left, 250, poly, port) ! port == declare port(name, left, 70, poly, left, 270, poly, port) ! ! ! net 20 ! port == declare port(name, left, 80, poly, right, 230, poly, port) ! port == declare port(name, left, 80, poly, left, -20, diffusion, port) ! ! ! net 19 ! port == declare port(name, right, 50, poly, left, 110, poly, port) ! port == declare port(name, right, 50, poly, left, 360, diffusion, port) ! ! ! net 4 ! port == declare port(name, left, 140, poly, left, 280, poly, port) ! port == declare port(name, left, 140, poly, left, 240, poly, port) ! port == declare port(name, left, 140, poly, left, 210, poly, port) ! port == declare port(name, left, 140, poly, left, 180, poly, port) ! ! ! net 23 ! port == declare port(name, left, 230, poly, right, 320, poly, port) ! port == declare port(name, left, 230, poly, left, -10, diffusion, port) ! ! ! net 21 ! port == declare port(name, left, 260, poly, right, 200, poly, port) ! port == declare port(name, left, 260, poly, left, 350, diffusion, port) ! ! ! net 13 ! port == declare port(name, left, 290, poly, left, 370, diffusion, port) ! ! ! net 10 ! port == declare port(name, left, 300, poly, left, 390, diffusion, port) ! port == declare port(name, left, 300, poly, right, 210, poly, port) ! port == declare port(name, left, 300, poly, right, 150, poly, port) ! ! ! net 7 ! port == declare port(name, right, 0, poly, right, 40, poly, port) ! ! ! net 16 ! port == declare port(name, right, 20, poly, right, 100, poly, port) ! ! ! net 22 ! port == declare port(name, right, 130, poly, left, -30, diffusion, port) ! port == declare port(name, right, 130, poly, right, 160, poly, port) ! ! ! net 31 ! port == declare port(name, right, 170, poly, right, 250, poly, port) ! ! ! net 34 ! port == declare port(name, right, 190, poly, right, 280, poly, port) ! ! ! net 32 ! port == declare port(name, right, 240, poly, right, 260, poly, port) ! ! channelr(name, port, 2) %end ! start test ("A test of the channel-router") ! test channel %end !############################################################################### !# # !# T E S T 13 : A test of the ILAP bonding pad symbols # !# # !############################################################################### %begin %integer padinx, padoutx, padcloutx, padcloutclx, padinoutinx, padinoutoutx, padinoutenx start test ("A test of the bonding pads") padvdd print string (" Pad vdd : SX ="); write (sx("padvdd"),2) print string (" SY ="); write (sy("padvdd"),3) newlines (2) padgnd print string (" Pad gnd : SX ="); write (sx("padgnd"),2) print string (" SY ="); write (sy("padgnd"),3) newlines (2) padin (padinx) print string (" Pad in : SX ="); write (sx("padin"),2) print string (" SY ="); write (sy("padin"),3) print string (" X ="); write (padinx,2) newlines (2) padout (padoutx) print string (" Pad out : SX ="); write (sx("padout"),2) print string (" SY ="); write (sy("padout"),3) print string (" X ="); write (padoutx,2) newlines (2) padclout (padcloutx, padcloutclx) print string (" Pad cl out : SX ="); write (sx("padclout"),2) print string (" SY ="); write (sy("padclout"),3) print string (" X ="); write (padcloutx, 2) print string (" CL X ="); write (padcloutclx,2) newlines (2) padinout (padinoutinx, padinoutoutx, padinoutenx) print string (" Pad in out : SX ="); write (sx("padinout"),2) print string (" SY ="); write (sy("padinout"),3) print string (" IN X ="); write (padinoutinx,2) print string (" OUT X ="); write (padinoutoutx,2) print string (" EN X ="); write (padinoutenx,2) newline %end !############################################################################### !# # !# T E S T 14 : A test of the automatic pad placement # !# # !############################################################################### %begin %const %integer dwid = 2, mwid = 8 { Diffusion and Metal widths } %const %integer yh = 80, xsep = 50 %const %integer chip no = 1 { The CIF symbol number of the external symbol } %const %integer max port = 14 %record (connf) %array ports (1:max port) %integer i start test ("The ILAP Pad Placement routine") EXTERNAL SYMBOL SPEC ("Chip", chipno, 0, 0, 6*xsep, yh) fill port (ports(1), vdd pad, left, yh//2-mwid//2, mwid, metal) %for i = 1, 1, 5 %cycle fill port (ports(i+1), in pad, top, i*xsep, dwid, diffusion) %repeat fill port (ports(7), gnd pad, right, yh//2-mwid//2, mwid, metal) fill port (ports(8), cl out pad cl, bottom, 5*xsep, dwid, diffusion) fill port (ports(9), cl out pad, bottom, 4*xsep, dwid, diffusion) fill port (ports(10), out pad, bottom, 3*xsep+xsep//2, dwid, diffusion) fill port (ports(11), in out pad en, bottom, 3*xsep, dwid, diffusion) fill port (ports(12), in out pad out, bottom, 2*xsep, dwid, diffusion) fill port (ports(13), in out pad in, bottom, xsep, mwid, metal) fill port (ports(14), out pad, bottom, 0, dwid, diffusion) PLACE PADS ("Full Chip", "Chip", ports, max port) %end !############################################################################### !# # !# T E S T 15 : A test of the ILAP symbols for annotation # !# # !############################################################################### %begin %integer i %string (255) characters start test ("A test of the symbols for annotation") characters = "" %for i = 33, 1, 126 %cycle { All printable Ascii Characters } characters = characters.to string (i) characters = characters.snl %if i&15=15 %repeat text ("chars", characters, 850, 700) crest ("Crest", 275, 350) copyright ("Copyright", 275, 350) symbol ("areas") layer (red) box (275, 0, 550, 350) box (0, 700, 850, 1400) end symbol symbol ("annotation") draw ("chars", 0, 700) draw ("crest", 275, 0) draw ("Areas", 0, 0) end symbol %end !############################################################################### start test ("") give statistics finish %end %of %program