!Lance transmit test
%begin
%option "-nons-low"
%include "inc:util.imp"
!include "ether:lance.inc-list"
%include "ether:ethutil.inc-list"

@16_106c %integer ipl3 vector
%integer oldvector
%integer pr=0,pt=0

%conststring(17)our dte = "AA-00-03-01-17-37"
%conststring(17)vms dte = "FF-FF-FF-FF-FF-FF"
%bytearray dte(1:6)

%record(ibf)ib
%record(drf)%name rring,tring

@16_fe0000 %half lance address register, lance data register

%routine wcsr(%half r,v)
  lance address register = r
  lance data register = v
%end

%integerfn rcsr(%half r)
  lance address register = r
  %result = lance data register
%end

%routine setup data structure
%integer i
%record(df)%name d
  ib = 0
  set dte(dte(1), our dte)
  convert dte to halfwords(dte(1), ib_pa0)
  rring == new ring
  tring == new ring
  point(ib_highrad,ib_lowrad,rring)
  point(ib_hightad,ib_lowtad,tring)
  ib_tcount = 16_e0
  ib_rcount = 0
  %for i = 0,1,127 %cycle
    d == tring_desc(i)
    d = 0; d_minus = -512
    point(d_highad,d_lowad,new buffer)
  %repeat
  d == rring_desc(0)
  d = 0; d_minus = -512
  point(d_highad,d_lowad,new buffer)
%end

%routine setup device
%half l
%byte h
  point(h,l,ib)
  wcsr(0, c stop)
  wcsr(1,l)
  wcsr(2,h)
  wcsr(3, bswp)
  wcsr(0, c init ! c strt ! c inea)
%end

%predicate it is due
%owninteger timer=0
%true;never:
  %if cputime>timer %start
    timer = cputime %if timer=0
    timer = timer+250
    %true
  %finish
  %false
%end

%routine scan tring
%integer i
%record(bf)%name b
%record(df)%name d
%ownhalf seqno = 0
%owninteger getpos=0,putpos=0
  %while getpos#putpos %cycle
    d == tring_desc(getpos)
    %if d_control & t own = 0 %start
      %if d_control # t stp ! t enp %start
        printsymbol('T'); phex2(getpos); printsymbol(':'); phex2(d_control)
        space; phex4(d_plus); newline
      %finish
      getpos = (getpos+1)&127
    %finishelseexit
  %repeat
  %if it is due %start
    d == tring_desc(putpos)
    %if d_control & t own = 0 %start
      printsymbol('T'); phex2(putpos); space; phex4(seqno); space
      phex(addr(d)); newline
      b == buffer of (d)
      set dte(b_ddte(1),vmsdte)
      set dte(b_sdte(1),ourdte)
      b_decpty = 16_0806
      b_isolength = 16_0900
      b_data(1) = seqno&255
      b_data(2) = seqno>>8
      seqno = seqno+1
      b_data(i) = i %for i = 3,1,9
      d_control = t own ! t stp ! t enp
      putpos = (putpos+1)&127
    %finish
  %finish
%end

%ownhalf intcsr=0,idon=0,rint=0,tint=0

%routine intwait
! *move.w #16_2000,d0; *trap#0; *stop #16_2000; *mtsr #0
  intcsr = lance data register
  idon = intcsr
  rint = intcsr
  tint = intcsr
%end

%owninteger lives=9

%onevent 0 %start
  lives = lives-1
  %if lives>=0 %start
    %if event_sub=2 %start
      printstring("Bus error at "); phex(event_extra); newline
    %elseunless event_sub=1
      printstring("Event 0 "); write(event_sub,1); newline
    %finish
    write(pr,0); write(pt,1); printstring(" R T"); newline
    phex4(intcsr); space; phex4(lance data register)
    printstring("Int Csr"); newline
    wcsr(0,c stop)
  %finish
  ipl3 vector = oldvector
  %stop
%finish

->begin

handler:
  *move.w d0,-(sp)
  *move.w lance data register, d0
  *move.w d0,intcsr
  *and.w #(cbabl!ccerr!cmiss!cmerr!crint!ctint!cidon!cinea),d0
  *move.w d0,lance data register
  *move.w (sp)+,d0
  *rte

begin:

  printstring("Starting")
    oldvector = ipl3 vector
    ipl3 vector = addr(handler)
    setup data structure
    ib_mode = m prom ! m drx
    setup device
  newline

  %cycle
    intwait
    %stop %if testsymbol>=0
    %if intcsr& c err # 0 %or intcsr&(c rxon ! c txon) # c txon %start
      printstring("Int: "); phex4(intcsr); newline
    %finish
    %if idon & c idon # 0 %start
      idon = 0
      lance data register = (intcsr & c inea) ! c idon
    %finish
    %if rint & c rint # 0 %start
      rint = 0
      lance data register = (intcsr & c inea) ! c rint
      printstring("R INT ?"); newline
    %finish
    %if tint & c tint # 0 %start
      tint = 0
      lance data register = (intcsr & c inea) ! c tint
    %finish
      scan t ring
  %repeat
  
%endofprogram