$a left=0.7";page=+0.5";line=7";just=1
$a tab=0.25",0.5",0.75",1",1.25",1.5",1.75",2",2.6"
$d # = $z0.03"$x+7"$y+2.5"$x-7"$y-2.5"$z0$y+2.5"
$d bigdash = $x1.5"$z0.03"$x+4"$z0"
$f10=TimesR10
$f12=TimesR12
$f22=TimesB12
$f32=TimesI12
$f14=TimesR14
$f24=TimesB14
$f18=TimesR18
$f44=TimesR24
$d item = $i0 $44{$h($r-0.1[.])} $t1
$12
$b10
$l1m
$44(Microcoded Graphics Interpreter)
$b4
$l1m
$18(Computer Structures 1984-85)
$b4
$l1m
$18(Microprogramming exercise)
$b20
$l1m
$32(Igor Hansen, room 3418)
$b24
$l0m
Department of Computer Science
University of Edinburgh




April 1985
$n
$a pageno=1
$18(Introduction)
$p1
The purpose of this exercise is to give you an opportunity of doing some 
experiments in the area covered by the lecture course Computer Structures I.
As it is not possible to cover all of the course subject area in a single
exercise, it was necessary to choose a part of it, starting immediately
below the lowest level of your current practical experience (assembly
language programming).
$p1
The task will be to write a microprogram that will 
interpret a simple subset of a graphics protocol (machine language level)
running on a specialised graphics hardware (microprogramming level).
The microcode
is almost completely horizontal, which gives direct control over the
separate functional blocks of the microprogrammed hardware.
$p1
The exercise is based on a 2-processor configuration of the APM,
where a dedicated, microprogrammed graphics
processor performs specialised tasks on behalf of the user processor.
The configuration of the system is shown below.
$b40
$l1m
$22(System configuration)
$p1
The description of the suggested protocol is given in the next chapter,
followed by the description of the graphics hardware.
$22(You should implement at least a subset of the protocol which will
allow you to display and manipulate multiple windows with single-font 
text in them.)
This will also require writing of a small demonstration control program.
$p1
If you are very keen on implementing something else, your own suggections
will be welcome with guarded enthusiasm and are subject to initial scrutiny.
$n 
$b10
$18(Submission)
$p1
This is to consist of the following:
$b1
$a indent=1
$b0 $item Demonstration of the working system (timetable to be announced)
$b0 $item Listing of well commented source of your microcode
$b0 $item A document containing detailed description of how your 
microcode works and how to run the demonstration.
You should also describe the protocol which you have implemented.
$a indent=0
$b5
$l1m
$22(Remember to permit all the necessary files!)
$b5
$bigdash
$b1 $l1m
$24(Deadline: 10:00, Friday, 31 May 1985)
$b0.5
$bigdash
$n
$l1m
$44(Graphics interpreter)
$b1
$18[Introduction]
$p1
This document describes a simple universal interface
between the applications programs, system utilities and user interface
modules on one side and the graphics support component of the system
on the other.
Such structured hierarchical graphics interface should fit easily into a 
variety of applications through supporting structured hierarchical dependencies
of objects both between and within the applications. 
It which attempts to provide flexible workspaces for the
individual applications while presenting a manageable and uniform
front to the graphics support subsystem. 
Several similar approaches have been suggested e.g. in [Foley 82] and 
[Lantz 84] but with a limited number of practical implementation
examples and less emphasis on their application to general interactive
computing environment. Recently work has been started on defining a standard
for a similar type of interface: Programmer's Hierarchical Interactive Graphics
Standard (PHIGS).
$p1
The interface is a directed graph, residing in the main system memory
where client processes in the system can manipulate their own allocated
sections on one side and a separate evaluation process caters
for the creation of the resulting images on the other as shown in a
paraphrase of a windowing system below. 
In other words, the evaluation process
can be viewed as a function taking the graph as an argument and producing
the image as a value. 
$b1
#
$p1
The top part of the graph is usually under the supervision of the system window
manager, while its exit edges provide linkage to applications subgraphs
running within their allocated subwindows. Such hierarchy may reoccur 
recursively
where an application may have its own subwindow manager maintaining its
menu, workspace and other areas of activity.
$p1
The image is computed through a depth-first scan of the descriptor structure,
where for each of the nodes, its local evaluation environment is saved,
prior to following any of the downwards edges and subsequently restored 
on return. The ordering of the exit edges defines the eventual overlap of
the graphical objects created by their execution.
Evaluation is terminated after the execution along the last vertical
edge of the node, at which it was invoked, thus allowing nested invokation
of selected substructures.
$p1
The speed of generating new images is strongly
dependent on the complexity of the graph and
on whether the evaluation process has to share the processor with other
processes, or it can have its own customised evaluation engine.
Depending on certain properties of the graph, like being acyclic or even
a tree, various optimisation techniques allow for only parts of the
graph to be scanned, still yielding a valid picture.
$n
$18(Graph construction)
$p1
The graph is constructed out of fixed-format nodes with two exit edges:
a $32(vertical) and a $32(horizontal) one. The vertical
edge is used to represent image hierarchy and the horizontal edge
supports linkage of multiple image components at the same level of
hierarchy.
$p1
Leaf nodes in such a directed binary graph i.e. those with no vertical 
exit edges are generally
responsible for the final drawing operations, and they can invoke 
operations like filling a polygon, drawing a stright line, drawing a
string of characters etc. These are executed with the necessary current
environmental attributes like: colour, font, scaling, clip boundaries etc. 
Some of the drawing
operations can have impact on the environment, like deposition of
character strings moves the working coordinates along the string baseline.
Non-leaf nodes are generally responsible for the composition of the picture
out of subordinate ones as well as for the necessary modifications of the
environment, like coordinate manipulations, colour and font selection etc.
Some of these operations, like moving or scaling are cummulative
along the vertical paths in the graph; others like font or colour selection
are nested.
There are also some general control nodes, which allow the user
to exercise control over the evaluation process.
$b1
#
$b1
$22(Format of the node)
$p1
Each binary node consists of 11 consecutive 16-bit half-words, where
the first two bytes contain the instruction code and the execution flags
of the node. They are followed by a long-word of argument field, and
then two long-words, where on exit, the evaluation process deposits the 
relative
dimensions of the bounding box for the image subordinate to the node.
These dimensions are relative to the environmental working
$32[(workX,workY)] coordinates on the entry to the node. 
The argument field can contain
a 32-bit pointer, two 16-bit geometrical or indexing arguments, or
for some single-argument operations only the first half-word is taken into
account.
The last two long-words contain downwards and rightwards pointers of
the exit edges, with execution flags $32[Down] and $32[Right] indicating their
validity. Flag $32[Pointer] when 1 represents indirection in fetching
of arguments.
$p1
We will describe further details of the nodes while presenting a number of
example applications. 
In all illustrations, nodes will be denoted with their associated opcodes
and those of the flags, which are set to 1. Values of 1 for the
$32[Down] and $32[Right] flags are indicated by the presence of the 
corresponding exit edges.
$n
$18(Example I: A leaf cell editor for VLSI design)
$p1
VLSI design systems are geared towards the management of complex,
integrated circuit designs. By the end of this decade, using available
technology, Mead [Mead 80] compares the design of integrated circuits 
with the complex task of designing an urban density road network the
size of an entire continent. The scope for error in such a project, if no 
proper tools are available, is
immense. Current fabrication technology also imposes a constraint on the
number of iterations designers can make to their circuit layouts as financial 
expenditure increases on each iteration.
$p1
Management is currently handled by a process of abstraction, i.e. 
of hierarchical structuring of the chip design into manageable "cells". Each
cell can in turn be individually created with geometric design rule checking
applied at each separate stage. A composition tool, either graphic or
textual, is then applied to
put together individually designed cells and form the overall design.
$p1
[Gray 79], [Buchanan 80], [Whitney 81], [Rees 83] have
proposed a methodology of circuit design based on such a hierarchical approach.
Recognising that there is a striking similarity between structured programming
techniques and VLSI design, we can apply the ideas of MODULARITY, (the
partition 
of the design into manageable "cells" with well defined functions and 
interfaces), HIERARCHY, (where modularity extends over partitioned levels of
the design), and ITERATION (the repetition of basic modules in both one and
two dimensions).
Using this design methodology, the complete design is created from a "top"
down" partition and a "bottom up" integration, with verification and 
simulation applied at various levels of the layout.
$p1
CAD may play an important role at all levels of the hierarchy, from composition tools
at root nodes of the design system down to "leaf cell" graphics editors.
In this section we provide a short presentation of
an editor for structured design of VLSI leaf cells which has been created
around the experimental graphics interface being presented in this paper. 
The editor is a component of a major design system [Rees 83] which
comprises a high level composition language, on-line geometric design rule
checking and automatic stretching and compaction of composition cells.
We outline some of the capabilities of the editor, with particular 
emphasis on the ease with
which we can produce a leaf cell cicuit design when tools such as the
appropriate representing data structure and its efficient intepreter are 
available.
$b1
$22[Editor design environment]
$p1
There are certain features of a circuit design environment which are fundamental
to the user. It must exhibit: fast interactive response, the ability to 
view the design at arbitrary geometric scales ( window management and 
multiple viewports ) together with a clean and comprehensive user interface.
The designer should feel intimately coupled to his design environment, with
both control and the ability to perform structured operations such as
viewing, panning and zooming at the touch of a button.
$p1
The editor is menu driven, and uses a mouse as the manipulating device. 
The mouse is used for pointing and editing individual 
objects on the screen, or as an area selector where whole groups of
objects are operated upon. The menu consists of representations of
components the designer can paint with (wires, transistors, contacts)
together with a set of high level functions (view, move, clone, input, 
output etc.)
which he can use to operate upon and compose design layouts. 
$p1
While operating within its own allocated window, the editor is a multiwindow
system in itself, with one menu and potentially more than one workspace
subwindow.
$n
$14(Ia: Building blocks)
$p1
The basic VLSI building blocks are wires, transistors and contacts. 
Using these primitive components it is possible to construct very large scale
circuit designs.
$p1
Wires are conventionally denoted as occupying certain "layers" on the silicon.
For a simple example of NMOS technology,
these layers are  polysilicon, diffusion and metal. 
Simple VLSI constructs, like transistors or contacts
are overlaps of the approriately sized and positioned "technological"
boxes. Using these objects more complex units such as
the "RAM cell" presented in the illustration can be constructed.
$p1
The fabrication process, however, still deals with a "flattened " design, 
and during fabrication objects such as contacts and transistors lose their
hierarchical structure and become merely "etchings" carved out of the
individual layers on the silicon wafer.
$p1
The colours selected are conventional circuit design, and the video planes
correspond directly with mask layers for
separate technological phases of the circuit production process.
$b1
#
$b1 $22(Simple structures)
$p1
There are two basic subwindows in the editor workspace area: one containing
the menu, and the other providing the design workspace.
The menu is a horizontally linked structure of menu items, where
graphical symbols are hierarchical structures themselves allowing for 
rotation, changes of 
technological layers and dimensions of objects prior to planting them
into the design. 
The workspace can contain several subwindows, each offering an indepenently
controlled viewport into the design.
$p1
Node $22(Move)(X,Y) modifies current environmental working coordinates
by (X,Y), prior to passing them down the vertical edge. Nodes $22[Box](X,Y)
and $22[Line](X,Y) draw a box and a line of size (X,Y) respectively,
starting from
their current working coordinates. Line drawing node has also a 
$22[Move](X,Y)
node effect on the environment, allowing sequences of lines to be drawn,
through vertical composition of such nodes.
Node $22[Colour](newcolour) defines the drawing colour for its subordinate
subgraph and node $22[Planes](enable mask) defines video planes with
permitted write operations.
Node $22[String](stringpointer) draws in current font and colour a 
string of characters starting from the current (workX,workY) to the right.
$p1
The transistor above has been built out of appropriately positioned
($22[Move]) boxes ($22[Box]) of diffusion ($22[Plane](diffusion))
and polysilicon ($22[Plane](polysilicon)).
$n
$14(Ib: Modularity and "Recipies" for cells)
$p1
The editor allows the user to create 
general descriptions of component structures
where subsequently they can be 
invoked with individual parameters for each instantiation.
$p1
The building blocks in circuit design are described both in terms of their
component structure and their geometric attributes, like size, shape and
orientation. For a
transistor we may have either an "etpx" (polysilicon in the x-direction)
or an "etpy" (polysilicon in the y-direction). Both these objects
share the same component structure but possess unique positioning parameters. 
We may think of an analogy
of a "recipe" which describes how to construct an object
and a list of "ingredients" which uniquely define each object type. By
partitioning the component description in this fashion it is possible to
perform geometric transformations such as scaling and rotation without
having to generate an entire component data structure each time. We merely
provide a new list of ingredients.
$b1
#
$b1 $22(Argument arrays and Indexing)
$p1
Nodes in the structure can obtain any of their two 16-bit arguments
through indexing into the current environmental argument array.
Execution flags $22[indexA] and $22[indexB] indicate whether
the first and the second half-word of the argument (possibly obtained
indirectly for $22[Pointer]=1) are the final arguments or indexes into
such array.
$p1
The array itself is declared by a node
$22[Setarguments](array pointer) where the new array pointer replaces
the one inherited from above for the subordinate subgraph of the declaration
node.
The construct provides the subgraphs which can be used like drawing
procedures in several places in the graph.
$p1
In the example above, the fixed-dimensions description of a transistor
from the previous page has been replaced by a "recipe" for a simple transistor,
where explicit dimensions have been replaced by indexes into a fixed-format
array. Various effects like rotation and size variations can be obtained
through appropriate swopping or variation of values in the individual
declarations of argument arrays prior to "calling" the transistor drawing graph.
$p1
The graph is no longer a tree, but it still remains acyclic.
$n
$14(Ic: Replicated composition)
$p1
Examining a very large scale integrated circuit layout one observes
that it consists of clearly distinguishable cells (memory cell, 
ALU cell, data path cell etc.. ). There is also a certain 
regularity of pattern within each cell itself. This regularity is created
by a repetition of basic cell subsystems, a prime example being the generation 
of a memory cell. Here the designer defines a basic single bit memory 
subsystem (seen here left top in the background)
and subsequently creates a complete memory cell by abutted replication
of the subsystem cell in both X and Y directions (top subwindow).
A programming analogy is the 2-dimensional array and the algorithm
analogous to nested iteration cycles.
Such nested, 2-dimensional composition will usually incorporate circuitry
required at the edges of the array. In the example
the ram interface cell has been designed and deposited on the right after each
iteration in the X direction (bottom subwindow). 
$p1
This ability to iterate in the X and Y direction is a very important tool
for the circuit designer. It facilitates design creation and alleviates the
task of verifying a complete circuit cell, since if the subsystem cell is
geometrically correct and the abutting interface is also correct then the
entire cell is geometrically correct. 
$b1
#
$b1
$22(Iteration)
$p1
Prior to descending along the vertical edge (for $22(Down)=1) the evaluation
process checks whether the $22(iteration) index in the current environment
is greater than zero and if not, the downward evaluation is not entered.
There are two nodes that control the value of the $22(iteration) index in
the environment. 
$22[Setiteration](number) provides nested presetting of the index
and $22[Deciteration] decrements it along the vertical edges.
$p1
In order to perform an iterated invokation of a subgraph (here 
of a subgraph drawing a RAM cell) we have to set the iteration index
above the graph and then create an iteration loop with decrementation of
the index in it. In the example, a $22[Move] node is placed immediately
to the right of the cell, allowing the cells to be placed side by side.
It is followed downwards by a $22[Deciteration] node, pointing in turn
down back at the memory cell.
This whole construct is then connected to the interface cell on the right
and embedded in the Y iteration construct above it.
$b2
$14(Id: Virtual coordinates and design inspection)
$p1
Having adopted the structured design approach the circuit designer is free
to concentrate on individual leaf cell creation. These leaf cells can
be quite large and complicated and in most cases extend
beyond the domain of the visible design workspace. By providing functions
such as panning and viewing the editor offers a much larger virtual design
workspace and uses the graphics screen only as a viewport into the design. 
$p1
The designer may then, during an editing session, view and edit sections of 
the layout at arbitrary design scales. 
Although each of the design subwindows can show sections of the same design 
in different scales, the whole of the design is represented and manipulated
in its virtual coordinates, here being equal to 1/8 lambda 
(a conventional design dimension unit where its mapping onto real dimensions
reflects the resolution of production technology).
$p1
In the example the background window shows a simple 8x4 memory array
reduced 4x, the next window with 2x reduction allows inspection
of RAM cells abbutment and the top window, with 1.5x enlargement shows
the alignment details on the right edge of the array.
$b1
#
$b1
$22[Deferred scaling]
$p1
A $22[Dscale](factorX,factorY) declares the environmental deferred scaling 
factors in X and Y for the subordinate subgraph. The operation is not
cummulative and there should be no more than one such node in each vertical
path in the graph.
The factors provide independent scaling in both axes, and do not take
effect immediately, allowing for unscaled composition of objects in their
virtual coordinates. They are applied only by the final drawing nodes
prior to creating them on the screen. Within these nodes clipping
is performed still in virtual coordinates.
For that reason the only immediate effect of 
declaring a deferred scaling, remapping of the clipping
environment from above into the virtual coodinates below.
$p1
An inspection viewport into a design is created by vertically composed
declarations of its position ($22[Move]), size ($22[Clip]) and viewing
scale ($22[Dscale]). The node $22[Move](-vX,-vY) below expresses in
designs virtual coordinates the positioning of the left bottom corner
of the viewport. All the viewports share the same global design structure.
Such "geometrical" viewing should be distinguished from "structured"
viewing, where the viewport can point at the selected subgraphs within the
design (the oblong window on previous page was in fact drawn by pointing
just below Y iteration loop in the global design of RAM array).
$p1
It is also worth noticing that the presented order of $22[Clip] and
$22[Dscale] nodes fixes the physical size of the viewport, decreasing
the amount of details as scaling factors increase.
Swopping of these two nodes would result in a constant amount of detail
and a growing viewport as the clipping would now be defined in the design's
virtual coordinates.
$n
$18(Example II: Bounding boxes, cursors and pointers)
$p1
One of the major components of the screen in an interactive graphics
system is the representation of a pointing device and cursor operations,
marking the areas occupied by the selected objects.
$p1
In the example the pointer is implemented as a $22[Template](pointer)
drawing node, which takes a bit-map representation of a shape (here a hand)
in the memory and deposits it, with current colour, at the position 
indicated by the current working coordinates.
Normally, it will be placed under 
$22[Colour](pointercolour) and
$22[Move](mouseX,mouseY) nodes. Such constructs are usually placed as
the last horizontal link within the window structure. It may appear on
the very top of the graph, providing general pointing capability
on the screen. Others may be linked within the applications windows,
with appropriately zeroed and clipped mouse coordinates supplied as
arguments.
$b1
#
$p1
A $22[Cursor](cursorpointer) node provides a nested declaration of
a graph to be used for drawing cursors. Cursorpointer points at the
top of the graph, which assumes a predeclared 4-element argument array
with the format of a node bounding box information field.
$p1
The evaluation process upon return to the node from the downwards evaluation
updates the node bounding box information, being the cummulative effect of
executing the node and the subordinate graph.
This information is stored as dimensions relative to the
working coordinates upon entry to the node.
Having updated the bounding box information and
upon seeing execution flag $22[Cursor] set to 1 the evaluation process
calls the current cursor drawing graph with the environment in which the
current argument array had been replaced by the node bounding box
definition field.
$p1
The construct allows to create individual cursors for various applications
with manipulation of flags being the only cost of invoking them.
Text strings can be underlined on their baseline by a small downwards 
$22[Move](0,-1), vertically composed with $22[Colour](cursorcolour)
and two horizontally linked
$22[Line,idxA](0,0) and $22[Line,idxA](2,0) nodes.
To underline a string just below its lowest descendent it is enough
to add a vertically composed $22[Move,idxB](0,1).
Similarly, full background and framing cursors can be defined.
$p1
Bounding box information is also used by the VLSI editor for joining of
cells, where the $22[Move] positioning individual RAM cells
picks up its arguments from the top node of the cell.
Similarly, the positioning of the interface cells at the end of
X iteration loop obtains its Y argument from the node on top of the loop.
$p1
Variation in fonts is achieved through a nested $22[font](fontpointer)
node, which declares a pointer to an array of 256 short integers 
being offsets to templates of individual characters within the font.
$n
$18(Example III: Nested windows and structured addressing of objects)
$p1
All of the examples have been developed within nested windowing environments.
$b1
#
$p1
A window can be defined by specifying its relative position 
($22[Move](Xbase,Ybase)),
its size ($22[Clip](Xsize,Ysize)) and background colour ($22[Colour](background)).
The construct can be nested, where subwindows can be used to host
different areas of activity maintained by the application process within the
window.
$p1
The portrait of a dog in window 1 was brought in as a $22[Template] in yellow.
Window 2 contains two subwindows 2A and 2B, and the greyscale picture
in window 3 has been brought in by a $22[Pixels](pointer) node from
the main system memory. 
$p1
The task of identfying an object addressed by the mouse coordinates
can be split into two basic tasks. The first one is the identification of the
nodes in the graph with bounding boxes covering these coordinates.
It involves a fairly simple top-down scan of the graph, where its vertical
edges are followed only for the nodes containing the pointer address.
Such scanning creates vertical paths in the graph, where more than one
distinct path will be created for the pointer contained in more than one
hierarchically unrelated nodes. 
Example positioning of the pointer creates only one path, which is depicted
by invoking a framing cursor for all the nodes containing it.
Positioning of the pointer
on "W" in window 2B would create 3 such paths.
$p1
The second task is the identification of a node within the paths,
where the active window identity, and the application running
within it perform the final selection.
$n
$18(Example IV: Structured program display)
$p1
Another example is that of a structured display of programs, where the
language syntax tree has been mapped almost directly onto the
display graph.
$b1
#
$p1
Appropriate "recipe" subgraphs have been initially created to describe
the mode of printing basic strings. The keyword printing environment
has been defined as "times roman bold" in white, names 
have been declared as strings in red "times roman", comments as italicised
green strings and all the remaining syntactic tokens are printed in blue.
Each token has been declared once with its multiple appearances
implemented through pointers. 
$p1
The layout of the program on the screen is obtained through appropriate
pairing of syntactic constructs of the language with their
graphics structure definitions.
A block is a vertical composition of a $22[Begin] token with
an indented, vertically composed list of statements and an $22[End]
token at the bottom. Indentation is achieved through a $22[Move](indentstep,0)
node above the statements list. Such a construct when nested, allows
for nested indentation of program representation on the screen.
$p1
Having declared the cursor as a framing box it is possible now to
frame addressed syntactic nodes of the program through placing
$22[Cursor] flags on the corresponding nodes of its graphics representation.
Here the cursor is placed on the block under the $22[While] loop.
$n
$18(Example V: Dual buffering)
$p1
The system assumes the use of a dual buffering technique for most
of the applications, where a new image is being created outside the currently
visible area of the framestore, and upon completion is swopped onto the
screen during the nearest vertical flyback. The technique assumes 
framestore memory size to be at least twice the size of the amount
required to support one visible frame.
There are different methods of partitioning such memory: geometrically
in X or Y through framestore offset registers,
or by mapping different sets of planes into the video output.
$b1
$z0.03"$x+7"$y+4.8"$x-7"$y-4.8"$z0$y+4.8"
$p1
In the example two 768x512 pixel buffers are fitted one above the other
in a 1024x1024 framestore.
Top $22[SetXY](baseX,baseY) node of the structure places the absolute
evaluation coordinates (workX,workY) in relative (0,0) coordinates
of one of the frames. A $22[Clip](768,512) node below it protects
the neighbouring, displayed frame and points vertically to the image
definition graph.
Having completed evaluating the main graph, a $22[FlybackY] node
witholds the continuation to the right until the nearest frame
vertical flyback, when the $22[Pan](baseX,baseY) through
framestore offset registers puts the display area over the newly evaluated
frame. $22[SetXY] and $22[Pan] nodes indirect into a 2-element offset
definition, where location X remains at 0 and Y is alternatively swapped
between 0 and 512.
$n
$18(Arguments and data structures)
$b2
$a indent=1
$item All pointers are 32-bit integers, interpreted as absolute 
byte addresses in the machine address space.
$b1
$item Additive/subtractive arguments are represented as 16-bit 2's 
complement integers.
$b1
$item Scaling factors are signed 16-bit numbers with
binary point between bits 7 and 8 of the word.
$a indent=0  
$p1
There are a number of data structures that can appear as arguments in the
nodes.
$b1
$a indent=4        
$i0 pixelmap $t4 is represented by 2 16-bit words specifying the width and the
height of the map, followed by the map itelf, stored as width-long
sequence of 1 pixel-wide vertical lines; one byte per pixel.
Following the increasing addresses
of the representation pixels will be drawn on the screen from bottom upwards, 
with consecutive vertical lines appearing to the right of their predecessors.
$b1
$i0 template $t4 consists of a 4 half-words header followed by
the bitmap of the template.
The half-words 0 and 1 contain template offsets in X and Y from the current 
working coordinates and half-words 2 and 3 specify width and height
of the template. 
Offsets are primarily used for positioning templates of the
characters relatively to the baseline and the in-line horizontal positioning
coordinate. They will be usually 0 for non-character type templates.
The template itself is stored as 
(width/16 + 1)-long sequence of height-long vertical strips. Following the
increasing addresses in the representation, individual strips will be drawn
on the screen from bottom upwards, with most significant bits on the left.
Consecutive strips are placed to the right of their predecessors.
$b1
$i0 font $t4 is stored as a list of templates for individual characters.
Such list of templates is preceeded by an
array indexed by the codes of characters and containing pairs of short
integers.
The first integer in each pair
contains offset from the base of array to the template of the corresponding
character and the second contains the formatting width of the character.
Entries of 0 in the first element of the pair indicate characters for which
templates have not been defined in that particular font and their
occurence is used by the protocol as one of termination conditions 
when drawing character strings.
Width of the character represents the distance to the base of the
next character to the right.
$b1
$i0 arrays $t4 are always 1-dimensional short-integer arrays, with the
lowest element having index 0.
$a indent=0      
$b2
$18(Evaluation environment)
$p1
Each node is executed within the environment inherited from the previous node,
and it may modify this environment prior to passing it to the next nodes: down, to
the right or up.
$p1
The environment consists of:
$a indent=6
$b1 $i0 colour $t6 current colour for the subordinate drawing nodes
$b1 $i0 planes $t6 a mask of planes with enabled write operation for the 
subordinate drawing nodes
$b1 $i0 (workX,workY) $t6 a pair of current working coordinates
$b1 $i0 (bblX,bbbY) $t6 left-hand bottom corner of the image bounding box
$b1 $i0 (bbrX,bbtY) $t6 right-hand top corner of the image bounding box
$b1 $i0 (cblX,cbbY) $t6 left-hand bottom corner of the environmental clipping
box
$b1 $i0 (cbrX,cbtY) $t6 right-hand top corner of the environmental clipping box.
$b0
Clip boundaries are the intersection of all the clipping boundaries set by
the clipping nodes above the current position. Deferred scaling node
maps them (division) into the virtual coordinates of the subordinate image.
$b1 $i0 (basX,basY) $t6 absolute starting point of the evaluation.
$b1 $i0 (refX,refY) $t6 current (0,0) reference point for nodes using absolute
positioning coordinates.
$b1 $i0 (dscaleX,dscaleY) $t6 A deferred scaling 
factor provided to support virtual to physical coordinate transformation. 
Deferred factor is applied to the coordinates and arguments in drawing
nodes, thus alowing the construction of the image above them to be expressed
in the virtual design coordinates.
Deferred scaling factor applies immediately only to the inherited
clipping coordinates, where reverse scaling of environmental coordinate 
information allows to implement physical clipping of images expressed in virtual
coordinates. Clipping in virtual coordinates is achieved through
positioning deferred scaling node above the clipping nodes.
$b1 $i0 iteration $t6 factor which must be greater then 0 for the interpreter
to follow the vertical exit edge from the node.
$b1 $i0 fontbase $t6 pointer indicates the base of the current font to be
used in all the subordinate string drawing operations.
$b1 $i0 argument array $t6 points to a one-dimensional array of shortwords
which can be used as arguments in the subordinate graph.
Entering the same subgraph with different array of arguments, is similar
to the passing of arguments to a drawing procedure.
Such subgraph should contain appropriate index flags set
for the nodes to which such arguments are
to be passed and appropriate array indexing information in its argument fields.
$b1 $i0 cursor $t6 points to a graph
currently responsible for drawing of cursors. Nodes of such graph
will be usually designed to pick up arguments from the environment
which invoked the graph.
$a indent=0
$b2
$18(Summary of node format)
$b1
Byte 0 of half-word 0 contains the instruction code.
$b1
Byte 1 contains flags, part of which parameterize the execution of
the instruction or of its subordinate subgraph.
$b0
Flags (Optimise,Wait,Pointer,IndexA,IndexB,Cursor,Down,Right) correspond to
bits [7:0] of the byte.
$b1
$a indent=3
$i0 Optimise $t3 flag invokes optimised evaluation of the subordinate graph,
where the interpreter will follow only those vertical edges, where
the bounding box of the image is expected to intersect with the current 
clipping box.
Such evaluation, although fairly simple to maintain at the top level nodes
e.g. with multiwindow textersŽ”‘Grather–-than“just“one“bit“v‘’b"alues.‘^T‘’2o“a•±v“oid›-ha“ving˜to˜store˜more˜than˜one˜non-terminalŽ”‘Gand–ymore“than“one“rule“n•±um“bNīer›yw“e˜can˜use˜instead˜of˜ĒG˜Ęan˜equiv‘’b"alen“t˜am“biguousŽ”‘Ggrammar–žöincorpšNīorate“disam±biguating“rules“in“the“pro˜cessors“to“resolvš±e“the“am˜biguities.Ž”‘GAn–#5amš±biguous“grammar“alone“w˜ould“force“the“proNīcessors“to“store“man˜y“reductions.‘¾īButŽ”‘Gbš±y–żresorting“to“disam˜biguating“rules,‘šw˜e“can“select“a“reductixA $t3 flag when 0 indicates that argument A is directly accessible
immediately or through a pointer, depending on the Pointer flag.
IndexA=1 signals that the value obtained through such access
is the argument index in the current argument array 
(See the description of individual nodes for
the declaration of the current argument array). 
$b1
$i0 IndexB $t3 has the same function as IndexA but applies to argument B.
$b1
$i0 Cursor $t3 flag set to 1 results in temporary replacement of the
current argument array pointer with a pointer to the bounding box
coordinates of the node, followed by a call to the
current cursor drawing graph.
$b1
$i0 Down $t3 flag indicates that half-words 7 and 8 contain a valid pointer
to the first instruction of a chain in the subordinate subgraph.
For Down=0 the interpreter will execute return phase of the instruction
without entering the evaluation of the subordinate graph.
Down=1 will be ignored for the iteration index in the current environment
being 0.
$b1
$i0 Right $t3 indicates that half-words 9 and 10 contain a valid pointer
to the next of horizontally linked chain of instructions. 
Upon encountering Right=0
the interpreter will execute the "return" part of the instruction
which invoked the currently terminated chain. Right=0 encountered at
the level at which the evaluation was invoked will terminate the evaluation.
              
The flag can be used for temporary disabling of manipulated parts of the 
picture. When modelling execution of a command stream
the Right=0 marks the last instruction of the stream.
$a indent=0
$p1
Half-words 1 and 2 contain information about the arguments for the node,
subject to interpretation under flags Pointer and Index.
$p1
The node contains also the information about the bounding box of the
subordinate picture.
This information, depending on the invoked mode of evaluation can be:
$b1
$a indent=1
$item updated by the evaluation process through the evaluation of the
subgraph
$b1
$item used by the evaluation process during the optimised evaluation
where subordinate images with bounding boxes outside the clipping 
coordinates are not evaluated.
$a indent=0
$b1
Bounding box coordinates relative to the current working (X,Y) coordinates
of the interpreter are stored in half-words 3-6. Half-words (3,4) and
(5,6) contain (X,Y) coordinates of left-hand bottom and right-hand top
corners of the box.
$n
$18(Nodes of the graphics data structure)
$b1
In the following descriptions arguments
of operation are shown in $32(italics) and represent values
obtained from half-words 1 and 2 through appropriate interpretation of
flags Pointer and Index.
$b2
$14(Non-drawing, environment modification nodes)
$b1
$22(FONT)($32[fontbase])
$b0
The subordinate graph will use the font starting at $32[fontbase].
$b1
$22(COLOUR)($32[colour])
$b0
$32[colour] becomes the colour for all the subordinate drawing operations.
$b1
$22(PLANES)($32[mask])
$b0
Planes indicated by 1's in $32[mask] will be enabled for writing in the
subordinate graph.
$b1
$22(RASTER)($32[rasterpointer])
$b0
In the subordinate graph the raster at $32[rasterpointer] will be used as a 
raster by all the area-filling operations. The initialisation raster is:
(16,1,16_FFFF) resulting in complete fill of the area.
$b1
$22(CURSOR)($32[cursorpointer])
$b0
$32(cursorpointer) points the top node of the cursor drawing structure
for the subordinate nodes.
$b1
$22(ARGUMENT)($32[arraypointer])
$b0
$32(arraypointer) points to the first element (indexed 0) of the argument array
for the subordinate nodes
$b1
$22(CLIP)($32[sizeX,sizeY])
$b0
Clipping in a rectangle of size ($32[sizeX,sizeY]), starting from the
current position. As an environmental attribute subject to retrospective
inverse scaling by the deferred scaling node.
$b1
$22(REFPOINT)($32[refX,refY])
$b0
Current X and Y coordinates modified by $32[refX] and $32[refY] become
a reference (0,0) point for the absolute (X,Y) arguments used by the
subordinate nodes.
$b1
$22(MOVE)($32[modX,modY])
$b0
Current X and Y coordinates are modified by $32[modX] and $32[modY] 
respectively. $32(modX,modY) may have to be prescaled by the current
immediate scaling factors.
$b1
$22(MOVETO)($32[absX,absY])
$b0
Current X and Y coordinates are moved to $32[absX,absY] relative to the
current reference point.
$b1
$22(DSCALE)($32[factorX,factorY])
$b0
Declaration of deferred scaling. Excludes presence of any other scaling
nodes in any of the vertical paths containing this node.
$b1
$22(SETITERATION)($32[iteration])
$b0
Declares iteration index $32[iteration] for the subordinate picture.
During execution flag "Down" is ignored if iteration index in the
environment is 0.
$b1
$22(DECITERATION)
$b0
Decrements iteration index in the environment.
$n
$14(Drawing nodes)
$p1
Drawing nodes are responsible for the final drawing operations.
In most applications they will appear as leaf nodes (flag Down=0) and
the evaluation will subsequently move to the next horizontally linked node or
to the return phase of the node above.
$b1
$22(BOX)($32[Xsize,Ysize])
$b0
Fills with current colour a box of size ($32[Xsize,Ysize]), starting at current 
evaluation coordinates. Evaluation coordinates for X and Y are modified
by $32[Xsize] and $32[Ysize] respectively.
($32[Xsize,Ysize]) are subject to scaling by the cummulated immediate or by
the deferred scaling factors.
$b1
$22(BOXTO)($32[absX,absY])
$b0
Similar to $22(BOX) but the fill area is defined by its corners: one in
current evaluation coordinates and the other ($32[absX,absY]) away from
the current reference point.
$b1
$22(POLYGON)($32[argumentlist])
$b0
Fills with current colour a polygon starting at current evaluation
coordinates and outlined by consecutive relative movements specified in
in $32[argumentlist].
$b1
$22(LINE)($32[Xsize,Ysize])
$b0
Draws a straigh line from the current evaluation coordinates to a point
distant by ($32[Xsize,Ysize]).
$b1
$22(LINETO)($32[absX,absY])
$b0 Similar to $22(LINE) but in absolute coordinates
$b1
$22(TEMPLATE)($32[template])
$b0
A pattern defined by the template is filled with current colour at the
current evaluation coordinates. 
$b1
$22(PIXELMAP)($32[pixelmap])
$b1
$22(STRING)($32[stringpointer])
$b0
Draws in current colour and with current font a string of characters.
Interpretation continues up to a character defined as a terminator by
the selected font.
$b1
$22(VSTRING)($32[stringpointer]), $22(BSTRING)($32[stringpointer])
$b0
Draw strings of characters using fonts from VISUAL200 and Perkin Elmer
terminals.
$b2
$14(Control nodes)
$b1
$22(FLYBACKY)
$b0
Withholds execution of the following instruction till the beginning of the
nearest framestore vertical flyback. Most of the following instructions 
require such synchronization.
$b1
$22(COLOURMAP)($32[colourmappointer])
$b0
Consecutive locations of the framestore colourmap are loaded with the
consecutive store values starting at $32(colourmappointer). 
8-bit intensities for  red, green and blue
are represented by bits [7:0], [15:8] and [23:16] of 
consecutive 32-bit words.
$b1
$22(SETXY)($32[Xoffset,Yoffset])
$b0
Explicitly sets $22(X) and $22(Y) evaluation coordinates.
Intended for support of dual-buffering scheme with two such nodes
used alternately as entry points to the structure.
$b1
$22(PAN)($32[Xoffset,Yoffset])
$b0
Left-hand bottom corner of the display will is placed at 
(($32(Xoffset)/16)*16,$12(Yoffset)) in the framestore. Can be used with
$22(SETXY) and $22(FLYBACKY) to implement dual-buffering.
$b1
$22(DEPOSITENV)($32[environmentpointer])
$b0
This node deposits at the location indicated by the [environmentpointer]
the contents of its current working environment.
$b1
$22(PICKUPENV)($32[environmentpointer])
$b0
Partial evaluation of the structure starting from a chosen node
may be invoked through setting up the working environment to that of
the current environment of the node from the previous full evaluation.
$32[environmentpointer] will be usually the same as in $22(DEPOSITENV)
node which should preceed the chosen entry node in the structure.
Such optimised evaluation can be invoked when activities are
concentrated within the topmost windows.
$b1
$22(CALLMICRO)($32[microaddress])
$b0
Sections of new microcode can be invoked,
through a call to a chosen microcode location. This would usually
refer to additional, loadable microcode memory.
In case of partial replacement (e.g. when trying out new instructions)
proper care should be taken of the consistency of the stacks (main
and microinstruction one).
$b1
$22(CLEAR)
$b0
Resets the evaluation stack pointer. Should be invoked after abnormal
completion.
$b1
$22(REPORTADDR)($32[reportpointer])
$b0
Sets $32[reportpointer] as destination for $22[REPORT] nodes.
$b1
$22(REPORT)($32[reportvalue])
$b0
Will deposit $32[reportvalue] at the location $32[reportpointer].
Can be used to trace the progress of evaluation.
$b2
$18(Interaction between the user processor and the interpreter)
$p1
After initialisation, as well as after each completed evaluation the graphics
processor-interpreter puts itself into a wait state. 
$b1
The process requiring the evaluation should set up all the necessary
startup environment including the required action on completion 
(e.g. $22[REPORT] node) and then wake up the graphics processor through
a write into location E04000.
$b1
The processor picks up from the environment its starting execution pointer
and performs depth-first scan of the structure. It will halt upon completion,
upon encountering flag Wait=1 or upon invalid opcode.
$b2
$14(Startup environment)
$p1
Local graphics processor memory is under addresses 16_E0E000-16_E0FFFE
in the APM address space.
$b1
$a indent=9
$22($i0 address $t3 attribute $t9 description)
$b1
$i0 E0E000 $t3 Execution pointer $t9 Prior to evaluation should be loaded
with a pointer to the required entry node (or to the first command in stream
execution). During evaluation it contains the current execution pointer.
$b1
$i0 E0E004 $t3 Execution flags $t9
$b1
$i0 E0E006 $t3 Current colour $t9 Contains current colour.
$b1
$i0 E0E008 $t3 Current planes $t9 16-bit mask with 1's indicating planes
with enabled write operation
$b1
$i0 E0E00A $t3 Current X $t9 Current working X coordinate
$b1
$i0 E0E00C $t3 Current Y $t9 Current working Y coordinate
$b1
$i0 E0E00E $t3 Bounding box $t9 left X coordinate
$b0
$i0 E0E010 $t9 bottom Y coordinate
$b0
$i0 E0E012 $t9 right X coordinate
$b0
$i0 E0E014 $t9 top Y coordinate
$b1
$i0 E0E016 $t3 Clipping box $t9 left X coordinate
$b0
$i0 E0E018 $t9 bottom Y coordinate
$b0
$i0 E0E01A $t9 right X coordinate
$b0
$i0 E0E01C $t9 top Y coordinate
$b1
$i0 E0E01E $t3 base point $t9 X
$b0
$i0 E0E020 $t9 Y
$b1
$i0 E0E022 $t3 reference point $t9 X
$b0
$i0 E0E024 $t9 Y
$b1
$i0 E0E026 $t3 deferred scaling $t9 X scaling factor
$b0
$i0 E0E028 $t9 Y scaling factor
$b1
$i0 E0E02A $t3 Iteration index $t9 Iteration index can be explicitly set
or it can be decremented. When 0 it inhibits evaluation of the subgraph of
the node.
$b1
$i0 E0E02C $t3 current font $t9 Current font pointer contains the address
of the base of the current font definition.
$b1
$i0 E0E030 $t3 Argument array $t9 It is a pointer to the base of the current
argument array.
$b1
$i0 E0E034 $t3 Cursor $t9 Cursor pointer addresses a graph currently used
for drawing cursors. Such graph will usually contain indexed argument
references in the array defining the bounding box of the image.
$a indent=0
$n
$l1m
$44(Microprogrammed Hardware)
$b2
$18(The Processor)
$p1
The block diagram of the processor data path is shown below.
It consists of 2 major sections, each of them built upon 3 16-bit busses: two
for address and one for data.
$b51
$l1m
$22(Graphics processor - block diagram)
$b1
$a indent=1
$item The left section has a general data processing capability.
Its address busses: $32(lA[15:0]) and $32(lB[15:0]) support framestore's $22(X) and 
$22(Y) coordinate addresses. 
When concatenated, $32(lA[14:0]),$32(lB[15:0]) can be used to drive 
the APM system address bus $32(AD[31:1]). Only half-word accesses of
system address space are possible.
$b1
$item The right section is designed to support block moves of data and 
is capable of driving
its address buses:  $32(rA[15:0]) and $32(rB[15:0]) 
with consecutive values of one 32-bit
address, or as two separate 16-bit counters.   Right data and address lines 
support local memory with 8k bytes of ROM and 8k bytes of dual-ported RAM
available locally on the processor board. The right data bus
supports also APM system and framestore data transfers.
$a indent=0
$b1
Data can be transferred between the left and right counterparts of the sections.
$b2
$14(Left section)
$p1
The major component of the left section is a 16-bit wide general-purpose data 
path, built out of 4 AM29203 4-bit "superslices". 
These are supported by a carry-lookahead circuit and
an AM2904 status and shift control unit. Detailed functional descriptions of
these units are provided in the appendix to this document.
$p1
The AM29203 contains 16 16-bit dual-ported registers, where ports A and B can be
output onto busses $32(lA[15:0]) and $32(lB[15:0]) for the values of microword 
fields $32{lAs}=0 and $32{lBs[1:0]}=00 respectively.   
Value 1 on $32{lAs} drives the bus $32(lA[15:0]) with the contents
of the bus $32(rA[15:0])
and value 01 on $32{lBs[1:0]} drives $32(lB[15:0]) with $32(rB[15:0]).
Value 10 on $32{lBs[1:0]} injects a 16-bit $32{constant[15:0]} microword
field onto $32(lB[15:0]).
$p1
The data bus $32(lD[15:0]) can be driven by the output from AM29203 alu 
shifter,  for the field $32{ldatas[1:0]}=00.   
For $32{ldatas[1:0]}=01 left data bus picks up contents of its
right counterpart:  $32(Data[15:0]) and for 10,  it contains 
swopped bytes of the bus $32(lA[15:0]):  $32(lA[7:0]),$32(lA[15:8]).   
Control value 11 reads ($32[zero,carry,negative,overflow]) 
status bits from AM2904 onto $32(lD[3:0]).
$p1
Microcode bits $32{shiftrl} and $32{spsi[7:0]} constitute instruction 
bits $32([8:0]) for the AM29203 slices.
Bit $32{shiftrl} is also used as instruction bit $32{[10]}, controlling
the direction of shift in the shift linkage section of the AM2904.
$p1
Fields $32{rfmaA[3:0]} and $32{rfmaB[3:0]} provide register 
addresses for the AM29203  A and B register output ports.
Field $32{rfmaB[4:0]} is also used to address registers during write 
operations.
16 bottom registers, addressed by 0,$32{rfmaB[3:0]} 
are the internal registers of the AM29203 and data is written into them from
the bus $32(lD[15:0]).
The top 16 addresses provide access to framestore control registers, for which
the data has to be provided on $32(Data[15:0]).
Addresses: 10000, 10001, 10010 and 10011 provide write access
to colour, plane write enable, X display offset and Y display offset registers.
$p1
Microword fields $32{AM04i[12:11]}, $32{shiftlk[3:0]} 
and $32{AM04i[5:0]} provide instruction bits $32([12:0]) for the AM2904.   
This device provides the $32[carryin] signal 
to the ALU of the AM29203 and all the necessary linkage for shifts. 
It supports the necessary status information
and also generates a variety of condition signals for the sequencer.
The detailed functional description of the device is provided in the appendix.
Bits $32{AM04cemL} and $32{AM04ceuL}, when 0, 
enable the writes into the device's program
and microprogram status registers.
$p1
The AM2904 can generate on its condition output a variety of functions applied 
to the values of its 4 input lines and internal status bits.   All the status
information in the data path is fed into these inputs, and the multiplexing of
the conditions onto 4 inputs lines is controlled by the microword bits:  
$32{condsel[7:6]}.   
For those bits being 00, inputs $32[(Iz,In,Ic,Iovr)]
are connected
to the ($32[zero, negative, carryout, overflow]) outputs from AM29203.  
01 provides a vector ($32(dmaAdone,lD[4],dmaBdone,lD[7])),
$32(dmaAdone) and $32(dmaBdone) being the completion signals from the 
right segment DMA modules.
For 10 the testable vector is ($32(lD[0],lD[3],lD[2],lD[6])) and a 0 in a
vector ($32(0,Yblank,lD[1],lD[5])), selected by 11 provides a 
constant for unconditional operations of the sequencer.
$32[Yblank] when 1 indicates vertical blanking period in the framestore.
$n
$14(Right section)
$p1
Address busses $32(rA[15:0]) and $32(rB[15:0]) of the right section can be 
driven from
their designated DMA address generation units, or from their left counterparts.
The selection is controlled by values 0 and 1 of microword selection bits 
$32{rAs} and $32{rBs} respectively.
$p1
Both DMA address generation units share the bits $32{dmai[2:0]}, which 
control instruction lines $32([2:0]) of the AM2942 DMA address generation 
chips. Instruction
line $32([3]) to those devices is set permanently to 0. 
A 0 on bit $32{dmasel} 
assigns this instruction to the module on $32(rB) bus, while forcing an 
"enable counters"
operation in the module on bus $32(rA).   Value 1 on $32{dmasel} has the 
opposite action, with $32{dmai[2:0]} controlling the module on $32(rA).
Bits $32{dmaBcenL} and $32{dmaAcenL} are the complemented carry 
inputs to the counters in the units
and can be used to individually enable the counts in the modules.
For $32{dmamode} bit being 0 both address generators operate individually,  
with their completion signals: $32[dmaBdone] and $32[dmaAdone] indicating the 
completion of operation in each of the modules. 1 on $32{dmamode} joins the 
modules into one 32-bit
address generator, with bus $32(rA[15:0]) being the more significant extension 
of 
$32(rB[15:0]), $32{dmaBcenL} being the count enable bit and $32[dmaBdone] 
signalling the completion of transfer.
$p1
Right data bus $32(Data[15:0]) can be driven from local memory (memory read) for
$32{rdatas[1:0]}=00, from $32(lD[15:0]) bus for 01, or it can invoke a 
read operation from APM for $32{rdatas[1:0]}=10. 
$b1
$a indent=5
$i0 $22(Important:) $t5 All APM transfers both in master and slave
modes are 16-bits wide and are addressed from $32(lA[14:0]), $32(lB[15:0]).
$a indent=0
$p1
Data can be written from right data bus into local memory (memory write) for
$32{datad[1:0]}=00, into APM for 10, or it can be used to update 
(X,Y)=($32(lA[10:0]),$32(lB[10:0])) location in the framestore.
$b2
$14(Sequencer)
$p1
The data path is controlled by microprogram sequencer AM2910, which is a version
of an older device AM2909 with added on-chip nanocoding of its control signals.
The device is a 12-bit wide data path capable of addressing up to 4096 words
of microcode, 512 of which can be ROM-based on the processor board.
$p1
Microword field $32{seqi[3:0]} controls instruction bits $32{[3:0]} of 
the device.
0 on $32{srldL}
forces an unconditional load of data from the data input into the sequencer's
internal register.
The contents of these 12 data input lines to the AM2910 is controlled by the 
$32(PL')
output signal from the device, where a 0 selects $32{constant[11:0]} 
from the
microword and a 1 selects $32{Data[11:0]} from the right segment.   
See the appropriate data sheet for the behaviour of the $32[PL'] signal for 
different instructions.
$p1
The condition input to the sequencer comes from the AM2904.
$p1
The initilise signal forces a "jump to 0" instruction in the sequencer.
$n
$14(Summary of microword format)
$b1
$0
$l0
   ==================+========================+================================+
   mw[00]: const[0]  | constant for the       | constant for the lB bus of the |
   mw[01]: const[1]  | AM2910 sequencer       | data path                      |
   mw[02]: const[2]  |                        |                                |
   mw[03]: const[3]  |                        |                                |
   mw[04]: const[4]  |                        |                                |
   mw[05]: const[5]  |                        |                                |
   mw[06]: const[6]  |                        |                                |
   mw[07]: const[7]  |                        |                                |
   mw[08]: const[8]  |                        |                                |
   mw[09]: const[9]  |                        |                                |
   mw[10]: const[10] |                        |                                |
   mw[11]: const[11] |                        |                                |
   ------------------+------------------------+                                |
   mw[12]: const[12] |                                                         |
   mw[13]: const[13] |                                                         |
   mw[14]: const[14] |                                                         |
   mw[15]: const[15] |                                                         |
   ==================+=========================================================+
   mw[16]: lAs       | lA bus source: 0 port A of 16 general registers         |
                     |                1 rA bus                                 |
                     | This is overriden by access from outside, forcing       |
                     |  lAs[15:0] <= APM: 0,AD[31:17]                          |
   ------------------+---------------------------------------------------------+
   mw[17]: lBs[0]    | lB bus source: 00 port B of 16 general registers        |
   mw[18]: lBs[1]    |                01 rB bus                                |
                     |                10 constant from the microword           |
                     |                11                                       |
                     | This is overriden by access from outside, forcing       |
                     |  lBs[15:0] <= APM: AD[16:1]                             |
   ------------------+---------------------------------------------------------+
   mw[19]: rAs       | rA bus source: 0 A bus DMA module                       |
                     |                1 lA bus                                 |
                     | Access from outside forces rA[15:0] <= lA[15:0]         |
   ------------------+---------------------------------------------------------+
   mw[20]: rBs       | rB bus source: 0 B bus DMA module                       |
                     |                1 lB bus                                 |
                     | Access from outside forces rB[15:0] <= lB[15:0]         |
   ------------------+---------------------------------------------------------+
   mw[21]: ldatas[0] | lDATA bus source: 00 output from AM29203 alu shifter    |
   mw[22]: ldatas[1] |                   01 rDATA bus                          |
                     |                   10 lA[7:0],lA[15:8] (swopped bytes)   |
                     |                   11 2904: zero,carry,negative,overflow |
   ------------------+---------------------------------------------------------+
   mw[23]: rdatas[0] | rDATA bus source: 00 local memory[rB[15:0]]             |
   mw[24]: rdatas[1] |                   01 lDATA bus                          |
                     |                  *10 APM data bus [lA[15:0],lB[15:0]]   |
                     |                   11                                    |
   mw[25]: rdatad[0] | rDATA bus dest. : 00 local memory[rB[15:0]]             |
   mw[26]: rdatad[1] |                   01                                    |
                     |                  *10 APM data bus [lA[15:0],lB[15:0]]   |
                     |                   11 framestore [lA[15:0],lB[15:0]]     |
                     | Codings marked with "*" invoke appr. APM bus transfers, |
                     | where the data path is the master of the bus.           |
                     | All above are overriden by access from outside, forcing |
                     | READ : APM data bus <= local memory                     |
                     | WRITE: APM data bus => local memory                     |
   ==================+==================================+======================+
   mw[27]: spsi[0]   | 29203 instruction code                                  |
   mw[28]: spsi[1]   |       (see the appropriate data sheet)                  |
   mw[29]: spsi[2]   |                                                         |
   mw[30]: spsi[3]   |                                                         |
   mw[31]: spsi[4]   |                                                         |
   mw[32]: spsi[5]   |                                                         |
   mw[33]: spsi[6]   |                                                         |
   mw[34]: spsi[7]   |                                                         |
   mw[35]: shiftr\l  |                                                         |
   ------------------+---------------------------------------------------------+
   mw[36]: rfmaA[0]  | A register address (read only)                          |
   mw[37]: rfmaA[1]  |                                                         |
   mw[38]: rfmaA[2]  |                                                         |
   mw[39]: rfmaA[3]  |                                                         |
   ------------------+---------------------------------------------------------+
$n
$l0
   ------------------+---------------------------------------------------------+
   mw[40]: rfmaB[0]  | B register address                                      |
   mw[41]: rfmaB[1]  | rfmaB[4]: 0 general registers  1 framestore registers   |
   mw[42]: rfmaB[2]  |             (write & read)       (write only)           |
   mw[43]: rfmaB[3]  |     0000                         colour                 |
   mw[44]: rfmaB[4]  |     0001                         plane write enable     |
                     |     0010                         X display offset       |
                     |     0011                         Y display offset       |
   ==================+=========================================================+
   mw[45]: AM04i[0]  | AM2904 instruction bits [0:5]                           |
   mw[46]: AM04i[1]  |        (See the appropriate data sheet)                 |
   mw[47]: AM04i[2]  |                                                         |
   mw[48]: AM04i[3]  |                                                         |
   mw[49]: AM04i[4]  |                                                         |
   mw[50]: AM04i[5]  |                                                         |
   ------------------+---------------------------------------------------------+
   mw[51]: condsel[6]| select input to AM2904(Iz,In,Ic,Iovr)                   |
   mw[52]: condsel[7]| 00 (zero,negative,carryout,overflow)                    |
                     | 01 (dmaAdone,?,dmaBdone,?)                              |
                     | 10 (?,?,?,?)                                            |
                     | 11 (.GND,?,?,?)                                         |
   ------------------+---------------------------------------------------------+
   mw[53]: shiftlk[0]| AM2904 shift linkage code                               |
   mw[54]: shiftlk[1]|        (See the appropriate data sheet)                 |
   mw[55]: shiftlk[2]|                                                         |
   mw[56]: shiftlk[3]|                                                         |
   ------------------+---------------------------------------------------------+
   mw[57]: AM04i[11] | AM2904 instruction bits [11:12]                         |
   mw[58]: AM04i[12] |        (See the appropriate data sheet)                 |
   ------------------+---------------------------------------------------------+
   mw[59]: AM04cem'  | write enable' to program status register                |
   mw[60]: AM04ceu'  | write enable' to microprogram status register           |
   ==================+==================================+======================+
   mw[61]: dmai[0]   | AM2942 instruction code (AM2942 i[3] = 0)               |
   mw[62]: dmai[1]   |        (See the appropriate data sheet)                 |
   mw[63]: dmai[2]   |                                                         |
   mw[64]: dmasel    | 0  dmaB: dmai[2:0]         dmaA: enable counters        |
                     | 1        enable counters         dmai[2:0]              |
   ------------------+---------------------------------------------------------+
   mw[65]: dmaBcen'  | complemented carry-in for the counters in dmaB          |
   mw[66]: dmaAcen'  |                                           dmaA          |
   ------------------+---------------------------------------------------------+
   mw[67]: dmamode   | 0 dmaB and dmaA operate as separate modules             |
                     | 1 dmaA is the more significant extension of dmaB        |
                     |   dmaBcen' is the complemented carry-in                 |
                     |   and dmaBdone is the completion signal                 |
   ==================+=========================================================+
   mw[68]: seqi[0]   | instruction for AM2910 sequencer                        |
   mw[69]: seqi[1]   | (See the appropriate data sheet)                        |
   mw[70]: seqi[2]   |                                                         |
   mw[71]: seqi[3]   |                                                         |
   ------------------+---------------------------------------------------------+
   mw[72]: srld'     | 0: sequencer register/counter := sDATA[11:0]            |
   ==================+================================================+========+
   mw[73]: waitreq   | 1: wait request                                |        |
   ------------------+------------------------------------------------+ timer  |
   mw[74]: slow      |                                                |        |
   ==================+================================================+========+
$b2
$12
$n
$18(Framestore)
$p1
The framestore consists of 2 types of circuits:
$b1
$a indent=1
$item 
display memory circuit corresponding to a 1024x1024
array of bits for the display, together with an associated 16-bit video
shift register
$b0
$item 
memory control circuit, responsible for the timing of the
write operations
in the display memory as well as for displaying of its contents on the screen
$a indent=0
$b2
$14(Display memory)
$p1
There are 4 memory circuits on one board, and they can be configured as:
$b1
$a indent=1
$item
4 planes with 1024x1024 pixels at 25MHz
$b0
$item
2 planes with 2048x1024 pixels at 50MHz
$a indent=0
$b2
$14(Display memory control circuit)
$p1
The display memory control circuit can control frames with up to 16 planes 
(16 bits/pixel).
The interface to the circuit has the following form:  
$b1
$a indent=1
$item two 12-bit coordinate addresses: $32(X[11:0]) and $32(Y[11:0])
$b0 $item 16-bit data bus: $32(D[15:0])
$b0 $item handshake lines to implement synchronisation with the processor 
driving the framestore
$a indent=0
$b35
$l1m
$22(Framestore and its interface)
$p1
The circuit includes the following processor writeable frame control registers:
$b1
$a indent=1
$item $22(colour register) for holding the colour to be used during write
operations into the frame
$b0 $item $22(plane write enable register), holding a mask of planes 
with permitted write operation
$b0 $item $22(X offset register) specifying the horizontal position of 
the left edge of the monitor display window within the frame
$b0 $item $22(Y offset register) specifying the vertical position of the display
window within the frame
$a indent=0
$b1
Offset registers are used for selecting parts of a picture for display
when the frame size exceeds that of the monitor. They also permit the use
of a double-buffering technique during image calculation where the frame size
is at least twice as large as the viewable area.
$b1
A write access into the framestore puts the contents of the colour register
into all pixels indicated by 1's on framestore data bus, where bits 
$32(D[15:0]) are positioned from ($32{X[11:0],Y[11:0]}) to
($32{X[11:0]}+$32{15,Y[11:0]}) in the framestore.
$b14
(X,Y+5) $t3 : $0(11110000)
$b0
(X,Y+4) $t3 : $0(00001000)
$b0
(X,Y+3) $t3 : $0(01111000)
$b0
(X,Y+2) $t3 : $0(10001000)
$b0
(X,Y+1) $t3 : $0(10001000)
$b0
(X,Y) $t3 : $0(01110100)
$b14
$l1m
$12(A sequence of write operations to draw an "a" character)
$n
$18(Microcode assembler and microcode loader)
$b1
$14(Assembler)
$p1
There exists a simple microcode assembler, which allows to exercise detailed
control over the data path.
$p1
Comments are bracketed with a percent sign "$0(%)" and a leading 
$0(0) identifies hexadecimal representation of numbers.
$b1
The assembler requires:
$b1
$a indent=1
$item Declaration of microword format
$b0
The declaration is a list of microword field names, their associated widths
and default values. The declaration of the microword of the graphics
processor is given below and it can be also picked up from C:IBH:FORMDEF.
$b1
$0
$l0
    form const    (16)=   0,    % constant field %
         lAs       (1)=   0,    % left  A bus source select %
         lBs       (2)=   0,    % left  B bus source select %
         rAs       (1)=   1,    % right A bus source select %
         rBs       (1)=   1,    % right B bus source select %
         ldatas    (2)=   0,    % left  data bus source select %
         rdatas    (2)=   0,    % right data bus source select %
         rdatad    (2)=   1,    % right data bus destination select %
         spsALU    (5)=   1,    % AM29203 instruction bits <4:0> %
         spsdes    (3)=   4,    % AM29203 instruction bits <7:5> %
         shiftrl   (1)=   1,    % AM29203 instr bit <8> and AM2904 bit <10> %
         rfaA      (4)=   0,    % AM29203 port A register address %
         rfaB      (5)=   0,    % AM29203 port B and frame control registers %
         AM04ia    (6)= 034,    % AM2904 instruction bits <5:0> %
         condsel   (2)=   3,    % condition input to AM2903 multiplexer %
         shiftlk   (4)=   0,    % AM2904 instruction bits <9:6> %
         AM04ib    (2)=   0,    % AM2904 instruction bits <12:11> %
         AM04cemL  (1)=   1,    % AM2904 machine status register enable %
         AM04ceuL  (1)=   1,    % AM2094 micro status register enable %
         dmai      (3)=   7,    % AM2942 dma counter instruction bits <2:0> %
         dmasel    (1)=   0,    % A/B segment instruction select bit %
         dmaBcenL  (1)=   1,    % B segment or long AB dma count enable %
         dmaAcenL  (1)=   1,    % A segment dma count enable %
         dmamode   (1)=   1,    % one long/two short counters select %
         seqi      (4)=  14,    % AM2910 sequencer instruction bits <3:0> %
         srldL     (1)=   1,    % AM2910 register load %
         waitreq   (1)=   0,    % microcode wait bit %
         slowck    (1)=   1     % microcode clock speed %
$b1
$12
$item Definitions of microoperations
$b0
A useful starting set of microoperation definitions can be picked up from
C:IBH:HARDDEF, listed below.
$b1
$0
$l0
% address busses control %
def lAreg(a)   = lAs=0;rfaA=a
def lBreg(b)   = lBs=0;rfaB=b
def lBconst(c) = lBs=2;const=c
def lABreg(a,b)= lAs=0;lBs=0;rfaA=a;rfaB=b
def lAdma      = lAs=1;rAs=0
def lBdma      = lBs=1;rBs=0
def lABdma     = lAs=1;lBs=1;rAs=0;rBs=0
def rAdma      = rAs=0
def rBdma      = rBs=0
def rABdma     = rAs=0;rBs=0
def rAreg(a)   = rAs=1;lAs=0;rfaA=a
def rBreg(b)   = rBs=1;lBs=0;rfaB=b
def rBconst(c) = rBs=1;lBs=2;const=c
def rABreg(a,b)= rAs=1;rBs=1;lAs=0;lBs=0;rfaA=a;rfaB=b

% data busses control %
def lDalu      = ldatas=0
def lDdata     = ldatas=1
def lDswop     = ldatas=2
def lDzcno     = ldatas=3
let memory=0, lD=1, APM=2, frame=3
def read(s)    = rdatas=s
def write(d)   = rdatad=d

% processor control %
  % ALU functions %
  def aluspecial      = spsALU=0
  def aluhigh         = spsALU=1
  def lBplsNlAplsC    = spsALU=2
  def QplsNlAplsC     = spsALU=3
  def lAplsNlBplsC    = spsALU=4
  def lAplsNQplsC     = spsALU=5
  def lAplslBplsC     = spsALU=6
  def lAplsQplsC      = spsALU=7
  def lBplsC          = spsALU=8
  def QplsC           = spsALU=9
  def NlBplsC         = spsALU=10
  def NQplsC          = spsALU=11
  def lAplsC          = spsALU=13
  def NlAplsC         = spsALU=15
  def alulow          = spsALU=17
  def NlAandlB        = spsALU=18
  def NlAandQ         = spsALU=19
  def lAxnorlB        = spsALU=20
  def lAxnorQ         = spsALU=21
  def lAxorlB         = spsALU=22
  def lAxorQ          = spsALU=23
  def lAandlB         = spsALU=24
  def lAandQ          = spsALU=25
  def lAnorlB         = spsALU=26
  def lAnorQ          = spsALU=27
  def lAnandlB        = spsALU=28
  def lAnandQ         = spsALU=29
  def lAorlB          = spsALU=30
  def lAorQ           = spsALU=31
  % Special functions %
  def TCmult     = aluspecial;spsdes=2;shiftrl=0;shiftlk=15
  def TCmultlast = aluspecial;spsdes=6;shiftrl=0;shiftlk=15
  def TCdivfirst = aluspecial;spsdes=2;shiftrl=1;shiftlk=15
  def TCdiv      = aluspecial;spsdes=4;shiftrl=1;shiftlk=15
  def TCdivlast  = aluspecial;spsdes=6;shiftrl=1;shiftlk=3
  % ALU destination control %
  def lsrFtoYwr       = shiftrl=0;spsdes=1
  def lsr0FQtoYwr     = shiftrl=0;shiftlk=6;spsdes=3
  def asrFQtoYwr      = shiftrl=0;shiftlk=6;spsdes=2
  def lsrNFQtoYwr     = shiftrl=0;shiftlk=14;spsdes=3
  def FtoQY           = shiftrl=0;spsdes=6
  def lslFtoYwr       = shiftrl=1;spsdes=1
  def aslFtoYwr       = shiftrl=1;spsdes=0
  def aslFQtoYwr      = shiftrl=1;spsdes=2;shiftlk=6
  def lslFQ0toYwr     = shiftrl=1;shiftlk=6;spsdes=3
  def FtoY            = shiftrl=1;spsdes=4
  def FtoYwr          = shiftrl=1;spsdes=7
  % shift control %
  def shleft          = shiftrl=1
  def shright         = shiftrl=0
  % register addresses %
  def regA(r)         = rfaA=r
  def regB(r)         = rfaB=r

% control for AM2904 %
  % carry - in control %
  def Cin0            = AM04ib=0
  def Cin1            = AM04ib=1
  def CinZ            = AM04ib=2

% composite functions %
def bswopR1toR2(r1,r2) = lAreg(r1);lDswop;FtoYwr;regB(r2)
def CtoY(c)         = lBconst(c);lBplsC;Cin0;FtoY;lDalu
def CtoR(c,r)       = lBconst(c);lBplsC;Cin0;FtoYwr;lDalu;regB(r)
def CtoCR(c,r)      = CtoR(c,r);read(lD)
def R1toR2(r1,r2)   = lAreg(r1);lAplsC;Cin0;FtoYwr;lDalu;regB(r2)
def R1plsQtoR2(r1,r2)=lABreg(r1,r2);lAplsQplsC;Cin0;FtoYwr;lDalu
def R1plsCtoR2(a,c,b)=lAreg(a);lBconst(c);lAplslBplsC;Cin0;FtoYwr;lDalu;regB(b)
def R1minCtoR2(a,c,b)=lAreg(a);lBconst(c);lAplsNlBplsC;Cin1;FtoYwr;
                              lDalu;regB(b)
def RcompareC(r,c) = lAreg(r);lBconst(c);lAplsNlBplsC;Cin1;FtoY
def R1compareR2(r1,r2)=lABreg(r2,r1);lBplsNlAplsC;Cin1;FtoY
def R1minR2toR1(r1,r2)=lAreg(r2);lBreg(r1);lBplsNlAplsC;Cin1;FtoYwr;lDalu
def R1minR2toQ(r1,r2)=lABreg(r2,r1);lBplsNlAplsC;Cin1;FtoQY
def minR(r)         = lBreg(r);NlBplsC;Cin1;FtoYwr;lDalu
def R1plsR2toR1(r1,r2)=lAreg(r2);lBreg(r1);lAplslBplsC;Cin0;FtoYwr;lDalu
def incR1toR2(r1,r2)  =lAreg(r1);lAplsC;Cin1;FtoYwr;lDalu;regB(r2)
def R1andCtoR2(a,c,b)=lAreg(a);lBconst(c);lAandlB;FtoYwr;lDalu;regB(b)
def R1orCtoR2(a,c,b) =lAreg(a);lBconst(c);lAorlB;FtoYwr;lDalu;regB(b)
def CtoQ(c) = lBconst(c);lBplsC;Cin0;FtoQY
def RtoQY(r) = lAreg(r);lAplsC;Cin0;FtoQY
def RtoY(r) = lAreg(r);lAplsC;Cin0;FtoY
def RtolD(r) = RtoY(r);lDalu
def R1ashltoR2(r1,r2)=lAreg(r1);regB(r2);lAplsC;Cin0;aslFtoYwr;lDalu
def mematCtoR(c,r) = rBconst(c);read(memory);lDdata;regB(r);FtoYwr
def mematRtoR(r)   = rBreg(r);read(memory);lDdata;FtoYwr
def RtomematC(r,c) = rBconst(c);write(memory);RtoY(r);lDalu;read(lD)
def R1tomematR2(r1,r2)=rBreg(r2);write(memory);RtoY(r1);lDalu;read(lD)
def APMtoR(r)      = read(APM);lDdata;FtoYwr;regB(r)
def APMofR1R2toR2(r1,r2)=lABreg(r1,r2);APMtoR(r2)
def QtoAPM(MS,LS)  = lABreg(MS,LS);QplsC;Cin0;FtoY;lDalu;read(lD);write(APM)
def Qtoframe       = QplsC;Cin0;FtoY;lDalu;read(lD);write(frame)
def QtomematC(c)   = rBconst(c);QplsC;Cin0;lDalu;read(lD);write(memory)
def QtoR(r)        = QplsC;Cin0;FtoYwr;lDalu;regB(r)

% condition selection %
def IFTRUE  = condsel=3;AM04ia=53
def IFFALSE = condsel=3;AM04ia=52
def IFlD5   = condsel=3;AM04ia=54
def IFNlD5  = condsel=3;AM04ia=55
def IFlD1   = condsel=3;AM04ia=58
def IFNlD1  = condsel=3;AM04ia=59
def IFblankY  = condsel=3;AM04ia=62
def IFNblankY = condsel=3;AM04ia=63
def IFlD0   = condsel=2;AM04ia=52
def IFNlD0  = condsel=2;AM04ia=53
def IFlD6   = condsel=2;AM04ia=54
def IFNlD6  = condsel=2;AM04ia=55
def IFlD2   = condsel=2;AM04ia=58
def IFNlD2  = condsel=2;AM04ia=59
def IFlD3   = condsel=2;AM04ia=62
def IFNlD3  = condsel=2;AM04ia=63
def IFdoneA = condsel=1;AM04ia=52
def IFNdoneA= condsel=1;AM04ia=53
def IFlD7   = condsel=1;AM04ia=54
def IFNlD7  = condsel=1;AM04ia=55
def IFdoneB = condsel=1;AM04ia=58
def IFNdoneB= condsel=1;AM04ia=59
def IFlD4   = condsel=1;AM04ia=62
def IFNlD4  = condsel=1;AM04ia=63
def IFiZ    = condsel=0;AM04ia=52
def IFNiZ   = condsel=0;AM04ia=53
def IFiOVR  = condsel=0;AM04ia=54
def IFNiOVR = condsel=0;AM04ia=55
def IFiC    = condsel=0;AM04ia=58
def IFNiC   = condsel=0;AM04ia=59
def IFiN    = condsel=0;AM04ia=62
def IFNiN   = condsel=0;AM04ia=63

% sequencer control %
def JZ      = seqi=0             %unconditional jump to 0%
def CJS(t)  = seqi=1;const=t %conditional call at constant%
def JMAP    = seqi=2             %unconditional jump to Data%
def CJP(t)  = seqi=3;const=t %conditional jump to constant%
def PUSH(l) = seqi=4;const=l %psh & cond.load const.to cntr%
def JSRP(t) = seqi=5;const=t %call(condition): reg or const%
def CJV     = seqi=6             %conditional jump to Data%
def JRP(t)  = seqi=7;const=t %branch(condition): reg or const%
def RFCT    = seqi=8             %reg=0=>(pop&cont.)|jmp stck&r-1%
def RPCT(t) = seqi=9;const=t %reg=0=>continue|(jmp const&r-1)%
def CRTN    = seqi=10            %conditional return%
def CJPP(t) = seqi=11;const=t %conditional jump to const & pop%
def LDCT(c) = seqi=12;const=c %unconditional ld const. to reg.%
def LOOP    = seqi=13            %cond=>(cont.&pop)|jumpto stack%
def CONT    = seqi=14            %continue%
def TWB(t)  = seqi=15;const=t %cond=>(cont&pop)|(0=>t&pop|stk)%
def seqrld  = srldL=0

% composite functions %
def continue   = IFFALSE;seqi=3
def callatC(c) = IFTRUE;CJS(c)
def return     = IFTRUE;CRTN
def jumptoC(c) = IFTRUE;CJP(c)

% timer %
def wait    = waitreq=1

% DMA control %
let dmaAcup = 0
let dmaAcdn = 00404
let dmaWcdn = 0
def Bwrcr   = dmai=0;dmasel=0
def Awrcr   = dmai=0;dmasel=1
def Brdcr   = dmai=1;dmasel=0
def Ardcr   = dmai=1;dmasel=1
def Brdwc   = dmai=2;dmasel=0
def Ardwc   = dmai=2;dmasel=1
def Brdac   = dmai=3;dmasel=0
def Ardac   = dmai=3;dmasel=1
def Brein   = dmai=4;dmasel=0
def Arein   = dmai=4;dmasel=1
def Bldad   = dmai=5;dmasel=0
def Aldad   = dmai=5;dmasel=1
def Bldwc   = dmai=6;dmasel=0
def Aldwc   = dmai=6;dmasel=1
def Benct   = dmai=7;dmasel=0
def Aenct   = dmai=7;dmasel=1
def Bcnt    = dmaBcenL=0;dmamode=1
def Acnt    = dmaAcenL=0;dmamode=1
def longcnt = dmaBcenL=0;dmamode=0;dmai=7
def slowly = slowck=1
def fast = slowck=0
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$12
$item Source microprogram
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The following example sections of microcode contain some constant declarations
and an example graphics function.
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include formdef  % provide microword format definition %
include harddef  % provide definitions of microoperations %
% execution flags (new microoperations)%
def IFoptimise  = IFlD7
def IFNoptimise = IFNlD7
def IFwait      = IFlD6
def IFNwait     = IFNlD6
def IFNindirect = IFNlD5
def IFNindexA   = IFNlD4
def IFNindexB   = IFNlD3
def IFcursor    = IFlD2
def IFNcursor   = IFNlD2
def IFNdown     = IFNlD1
def IFNright    = IFNlD0
% registers %
  % control registers %
  let aregA   = 23,
      aregB   = 22,
      offsetY = 19,
      offsetX = 18,
      plwren  = 17,
      colour  = 16
  % data path registers %
  let stackpt = 15,       % stack pointer in local memory %
      coorY0  = 14,       % absolute current evaluation coordinate Y %
      coorX0  = 13,       %                                        X %
      coorY1  = 12,       % relative to Y0 %
      coorX1  = 11,       % relative to X0 %
      coorY2  = 10,
      coorX2  =  9,
      addrLS  =  8,       % address register: half-word address %
      addrMS  =  7,
      opcode  =  6,
      argB    =  5,       % argument registers %
      argA    =  4,aux4=4,aux3=3,
      R3=3,R2=2,R1=1,accum=0           %general registers%
% address constants %
  let myaddr = 104      % more significant half of processor bus address %
  % ROM %
  let maskbase    = 0,  bitbase     = 16,
      fontVISUAL  = 384,fontBANTAM  = 1792                     %resident fonts%
  % RAM %
  let RAMbase     = 4096,
      RAMtop      = RAMbase + 4096,
      exepointer  = RAMbase    ,   % current execution pointer %
      status      = RAMbase + 2,   % working status register %
      % environment %
      currink     = RAMbase + 3,   % drawing colour %
      currplan    = RAMbase + 4,   % planes enable mask %
      workX       = RAMbase + 5,   % current working coordinates: X %
      workY       = RAMbase + 6,   %                              Y %
      bblX        = RAMbase + 7,   % current bounding box: left   X %
      bbbY        = RAMbase + 8,   %                       bottom Y %
      bbrX        = RAMbase + 9,   %                       right  X %
      bbtY        = RAMbase +10,   %                       top    Y %
      cblX        = RAMbase +11,   % current clipping box: left   X %
      cbbY        = RAMbase +12,   %                       bottom Y %
      cbrX        = RAMbase +13,   %                       right  X %
      cbtY        = RAMbase +14,   %                       top    Y %
      iscaleX     = RAMbase +15,   % immediate scaling factor:    X %
      iscaleY     = RAMbase +16,   %                              Y %
      dscaleX     = RAMbase +17,   % deferred scaling factor:     X %
      dscaleY     = RAMbase +18,   %                              Y %
      iteration   = RAMbase +19,   % iteration index %
      currfont    = RAMbase +20,   % current font pointer %
      currargarray= RAMbase +22,   % current argument array pointer %
      currcursor  = RAMbase +24,   % current cursor-drawing structure pointer %
      reportloc   = RAMbase +26,   % reporting address %
      % auxiliary locations %
      APMdata     = RAMbase + 32,
      stackmarker = RAMbase + 33,
      rasterbuff  = RAMbase + 1024,
      stackbottom = RAMtop,            % pointer points at the topmost element %
      stacklimit  = stackbottom - 2048

% geometry of the screen %
let screenhight = 512,
    screenwidth = 48*16

begin:     CtoR(stackbottom,stackpt);wait
% ** instruction fetch ** %
evaloop:   mematCtoR(exepointer,addrMS)   % bring execution pointer %
           mematCtoR(exepointer+1,addrLS) % from local memory       %
           callatC($#shraddr)
           R1toR2(addrLS,opcode)          % fetch the instruction   %
           APMofR1R2toR2(addrMS,opcode);callatC($#incaddr)

% ** fetch from exepointer+2 and exepointer+4 into argA and argB ** %
           R1toR2(addrLS,argA)
           APMofR1R2toR2(addrMS,argA);callatC($#incaddr)
           R1toR2(addrLS,argB)
           APMofR1R2toR2(addrMS,argB);callatC($#incaddr)

           .......
           .......
           .......

% *** drawing a box *** %
drawboxC:  R1plsR2toR1(argA,coorX0)   % diagonal of the box %
           R1plsR2toR1(argB,coorY0)
           % sort the edges and expand environmental bounding box %
           R1compareR2(argA,coorX0);IFiN;CJP($#boxswopX)
           RtomematC(argA,bbrX)  % expand bounding box to the right %
           jumptoC($#boxYsort)
boxswopX:  R1toR2(coorX0,accum)  % swop coorX0 and argA for box to the left%
           R1toR2(argA,coorX0);rBconst(bblX);read(lD);write(memory)
           R1toR2(accum,argA)
boxYsort:  R1compareR2(argB,coorY0);IFiN;CJP($#boxswopY)
           RtomematC(argB,bbtY)  % expand bounding box upwards %
           jumptoC($#boxlclip)
boxswopY:  R1toR2(coorY0,accum)  % swop coorY0 and argB for box downwards %
           R1toR2(argB,coorY0);rBconst(bbbY);read(lD);write(memory)
           R1toR2(accum,argB)
           % clip the box while checking for intersection %
boxlclip:  mematCtoR(cblX,accum) % left clipping edge %
           R1compareR2(argA,accum);IFiN;CJP($#endcall)  % outside to the left %
           R1compareR2(coorX0,accum);IFNiN;CJP($#boxrclip)
           R1toR2(accum,coorX0) % clip on the left %
boxrclip:  mematCtoR(cbrX,accum) % right clipping edge %
           R1compareR2(accum,coorX0);IFiN;CJP($#endcall) % outside to the right %
           R1compareR2(accum,argA);IFNiN;CJP($#boxbclip)
           R1minCtoR2(accum,1,argA) % clip on the right %
boxbclip:  mematCtoR(cbbY,accum) % bottom clipping edge %
           R1compareR2(argB,accum);IFiN;CJP($#endcall)   % outside below %
           R1compareR2(coorY0,accum);IFNiN;CJP($#boxtclip)
           R1toR2(accum,coorY0) % clip on bottom %
boxtclip:  mematCtoR(cbtY,accum) % top clipping edge %
           R1compareR2(accum,coorY0);IFiN;CJP($#endcall) % outside above %
           R1compareR2(accum,argB);IFNiN;CJP($#boxdscal)
           R1minCtoR2(accum,1,argB) % clip on top %
boxdscal:  mematCtoR(dscaleX,R1) % deferred scaling in X %
           R1toR2(coorX0,accum);callatC($#scalmult)
           R1toR2(accum,coorX0)
           R1toR2(argA,accum);callatC($#scalmult)
           R1toR2(accum,argA)
           mematCtoR(dscaleY,R1) % deferred scaling in Y %
           R1toR2(coorY0,accum);callatC($#scalmult)
           R1toR2(accum,coorY0)
           R1toR2(argB,accum);callatC($#scalmult)
           R1toR2(accum,argB)
           R1minR2toR1(argA,coorX0);IFiZ;CJP($#endcall) % size of the box in X %
           R1minR2toR1(argB,coorY0);IFiZ;CJP($#endcall) % size of the box in Y %
           rBconst(dmaAcup+dmaWcdn);Bwrcr % set up DMA support for Y %
           rBreg(coorY0);Bldad
           rBreg(argB);Bldwc
           CtoR(16,R1)
           CtoQ(0FFFF)
boxhloop:  R1compareR2(argA,R1);IFiN;CJP($#boxlstrp)
boxvlo16:  lAreg(coorX0);lBdma;Benct;Bcnt;Qtoframe;IFNdoneB;CJP($#boxvlo16)
           R1minR2toR1(argA,R1);IFiZ;CJP($#endcall)
           R1plsR2toR1(coorX0,R1);Brein;jumptoC($#boxhloop)
boxlstrp:  rBreg(argA);read(memory);lDdata;FtoYwr;slowly % fetch write mask %
           RtoQY(argA)
boxvloen:  lAreg(coorX0);lBdma;Benct;Bcnt;Qtoframe;IFNdoneB;CJP($#boxvloen)
           jumptoC($#endcall)  

           ......
           ......
end
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$12
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All these have to be included in one source file explicitly or through
"include filename" construct.
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Assembler is invoked through command
HMD:NMU $32(SourceFilename) and will
produce loadable microcode under $32(SourceFilename.mu) .
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$14(Loader)
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Loadable microcode can be loaded into microcode RAM through
command 
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MLOAD $32(SourceFilename). Extension $32(.mu) is assumed
automatically.
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$14(Running and debugging)
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$a indent=4
$i0 reset $t4
A reset operation puts the processor into a WAIT state prior to execution
of the first microinstruction (at 000).
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$i0 execute $t4
A write into location 00D04000 is equivalent to pressing an "EXECUTE" key
on the front panel. After initialisation it should be done once in order
to start the processor. During the exercise this should be preceeded by loading
the dynamic microcode.
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$i0 single-step $t4 Single-stepping through instructions can be obtained
through setting their Wait execution flags and then using the writes into
00D04000 to activate evaluation of consecutive instructions.
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Wait states to single-step through microcode can be achieved by setting
to 1 the $32(wait) bit in the microwords of the required microinstructions.
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$22(Logic state analyser)
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One of the kits will have a logic state analyser connected to it.
It will minitor the addresses of the currently fetched microinstructions,
together with the value of the condition signal, under which these 
microinstructions were selected (condition input into AM2910).
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Instruction as how to use this device will be given when necessary.
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$b10
$l1m
$44(Data sheets for the devices)
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