wline; %stop
  %finish
  %trueif runflag=0
  ok = -1
  p = m_gla; p = p&\1 %unless p=1
  code = (header_main&65535)<<1+code
  run(code,p)
  %stop

%end{main}; %trueif main; %false
%end{loadmodule}

!   Diagnostics

%string(31)%fn nameof(%integer token)
%integer ls
%string(255)s
  transname(token,s)
  ls = length(s)
  %if ls>4 %start
    ls = ls-4 %if substring(s,ls-3,ls)=".MOB"
  %finish
  ls = 31 %if ls>31
  length(s) = ls
  %result = s
%end

%integerfn codestart(%record(mob header f)%name h)
%integer a
  and$or (tdrain\,double) -> purge\
u74 (.0,tfill\,.reset\,purge\) -> tempty\,tempty
$land$nor (tfill\,tdma\) -> setdouble
nand (setdouble,wcz\) -> setdouble\
u74 (.0,setdouble\,.reset\,tdrain\) -> double,double\
$lnand$or (tdrain\,double) -> teh\
$lnand$or (tdrain\,double\) -> tel\
$lnand$or (wcz\,tdmaing\) -> clrodd\

$ Receiver  (E->U)

nand(rdma,dmaing) -> rdmaing\
$lnor$and (rdmaing\,rdbr\) -> rdrain\
u125 (rempty\,erlt\) -> ed<7>
$lor$nand (ewlt\,eiowr\) -> ew1
$lor$nand (ewlt\,edack\<3>) -> ew2
nand (ew1,ew2) -> rfill\
and (edack\<3>,rempty) -> edrq<3>
$lnor$and (readcc\,.reset\) -> clrb9\
u74 (ea\<0>,clrb9\,?,ewlt\) -> rbit9\,rbit9
u74 (rbit9\,clrb9\,rfill\,rdrain\) -> rempty,rempty\
$lnor$and (rdrain\,.reset\) -> clrfull\
$lor$nand (rhalffull\,rdma) -> setrfull
u74 (rdma,?,clrfull\,rfill\) -> rhalffull,rhalffull\
u74 (setrfull,?,clrfull\,rfill\) -> rfull,rfull\
and (rfill\,rhalffull) -> rlfill\
nand (rbit9,rdma,rfull) -> setodd\

$ Interrupt request logic

$ rbit9\rdma + rbit9\rfull + rfull\rdma
$ reduces to rbit9\rfull + rfull\rdma
nand (rbit9,rfull\) -> rirq\1
nand (rfull,rdma\) ->  rirq\2
nand (tempty,tdma\) -> tirq\
$lor$nand (bcz\,tirq\,rirq\1,rirq\2) -> irq

$ Bus acquisition for Interrupt

nor (isack,.reset) -> clbr\
u74 (ie,?,clbr\,irq) -> br,?
inv (bgi\) -> bgi'
nand (bgi\,passbg) -> clrbgo\
nor (inting,.reset) -> clrisack\
u74 (br,clrbgo\,?,bgi') -> bgo\,passbg
u74 (br,?,clrisack\,bgi') -> isack,isack\
$land$nor (isack\,rssyn,rbbsy) -> setinting
and (rssyn,inting) -> intdone
nor (intdone,.reset) -> clinting\
u74 (.0,clinting\,?,setinting) -> ?,inting

$ DMA request logic

$land$nor (rdma\,rfull\) -> rdrq
$land$nor (tdma\,tempty\) -> tdrq
nor (rdrq,tdrq) -> drq\

$ Bus acquisition for DMA

$land$nor (drq\,dmaing,dsack) -> npr
inv (npgi\) -> npgi'
nand (npgi\,passnpg) -> clrnpgo\
nor (dmaing,.reset) -> clrdsack\
u74 (npr,clrnpgo\,?,npgi') -> npgo\,passnpg
u74 (npr,?,clrdsack\,npgi') -> dsack,dsack\
$land$nor (dsack\,rssyn,rbbsy) -> setdmaing
and (dmaing,rssyn) -> dmadone
nor (dmadone,.reset) -> cldmaing\
u123 (.0,setdmaing,cldmaing\,dmarc,dmac) -> dmaing,dmaing\
or (dmaing,dmaing) -> tmsyn   $ Deskew delay
u74 (rssyn,.reset\,?,dmaing\) -> ?,tmo

inv (pinit\) -> pinit
nor (rinit,pinit) -> .reset\
or  (pinit,rinit) -> .reset
u74 (.0,enint\,.reset\,disint\) -> ie,?
nor (.reset,tmo) -> clobber\
u74 (.0,settdma\,clobber\,bcz) -> tdma,tdma\
u74 (.0,setrdma\,clobber\,wcz) -> rdma,rdma\

u74  (rd<00>,setodd\,clrodd\,wbcr\)   -> bcr<00>,?
nand (min0,min1,min2,min3) -> wcz\
inv (wcz\) -> wcz
$land$nor (wcz\,bcr<00>) -> bcz
inv (bcz) -> bcz\

end