@newpage @Section@Label(Memory1) @IndexSecondary(Primary="Board", Secondary="Memory") @Index(Memory board) The standard memory board provides 512K bytes of parity checked volatile memory. The memory is based on 64K dynamic memory chips. To minimise the effect of cycle times and refresh overheads the board is internally organised as two interleaved banks. Approximate performance is as follows: @Begin(FileExample) Average access time (read and write):<230 ns Average cycle time :<260 ns Worst case access time :<550 ns @End(FileExample) @b[Switches and indicators:] @Begin(Format, Group) | |---- | [| MSD Address Select Switches. |---- | [| Selects the address of the memory within the |---- high order bits of the bus real address space. | [| The board is disabled if the least significant |---- digit is other than 0 or 8. | [| LSD |---- | | | | | | |---- | 0 | Access indicator. | 0 | Parity fault indicator. |---- |---- | - | Up position -Parity checking disabled. |---- Centre position - Checking enabled. | Indicator not latched. | Down Position - Checking enabled. | Indicator latched after single | fault. | In normal service this switch should ALWAYS | be in the bottom position. | The indicator may be cleared after a single fault | by moving the switch to the centre position before | returning it to the down position. | Parity checking should be disabled only when | running diagnostic hardware. | @End(Format)