{LANCE 10MHz Ethernet interface}
{State Machine for bus slave response timing}
{RWT 01/03/85}

5 {Inputs:}  reset ready' tac' sel read
4 {Outputs:} tac das' cs' write'
2 {State bits}

0: {Idle: wait for SEL without TAC}
  cs' = \(sel.tac'.\reset),
  das' = 1,
  write' = \(sel.tac'.\reset)+read,
  tac = 0,
  1 = sel.tac'.\reset;

1: {Select the chip (enabling RW' onto READ)}
  cs' = 0,
  das' = \(sel.\reset),
  write' = read,
  tac = 0,
  0 = \(sel.\reset),
  3 = sel.\reset;

3: {Perform the transfer (activate DAS), wait for READY}
  cs' = 0,
  das' = \read.\ready',
  write' = read,
  tac = \ready',
  0 = reset,
  2 = \ready'.\reset;

2: {Deactivate DAS, assert TAC, wait for TRQ (i.e. SEL) to go away}
  cs' = \sel,
  das' = \read+\sel,
  write' = \sel+read,
  tac = sel,
  0 = \sel+reset;

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