{
LANCE 10MHz Ethernet interface
State Machine for bus acquisition and interrupt transfer
RWT 20/03/85
}

{Input bits}  6

reset'  {a separate input saves the need for clearable latches}
hold'   {request from LANCE chip, indicating a wish to DMA}
intr'   {request from LANCE chip to alert the CPU}
cbr'    {request from another Fred-bus master that it wants the bus}
bgr'    {indication from arbiter that we have been granted the bus}
tac'    {indication from Fred-bus slave that a transfer has completed,
         used here (a) to hold off on bus acquisition (for robustness)
         and (b) to handshake the interrupt transfer}

{Output bits}  5

brq     {request to the arbiter for access to the Fred-bus}
itrq    {internal signal (Interrupt Transfer ReQuest), orred with
         DTRQ (DMA TRQ, derived from LANCE's DAS) to generate the
         Fred-bus's Transfer ReQuest signal}
hlda'   {indication to the LANCE that it has been granted control
         of the local bus.  Also used internally to enable bufties}
int'    {indication to internal logic to enable certain bufties for
         an interrupt bus transaction}
master' {MASTER is always the OR of HLDA and INT, used to enable those
         bufties common to DMA and INT transactions (in fact only A<31:24>)}

{State bits}  3

{State descriptions}

0:

{Idle state, interrupt armed.  Every other state contains a path to here
should RESET become active.  We wait here until we have been granted the bus.}

{We put out a bus request to the arbiter when we wish either to DMA
(HOLD is active) or to interrupt the CPU (INTR is active), provided
RESET is inactive}

brq = reset'.(\hold'+\intr'),

{In the interests of rubustness we do not optimise the response, and
guarantee that the internal acknowledge signals (HLDA and INT) are
kept inactive durring the first cycle in the next state}

hlda' = 1, int' = 1, master' = 1,
itrq = 0,

{When we have been granted the bus (RESET and TAC inactive, BGR active),
we proceed to state 4 (if we want to DMA: HOLD active) or to state 1
(if we want to interrupt: INTR active).  DMA takes priority.}

4 = reset'.tac'.\bgr'.\hold',
1 = reset'.tac'.\bgr'.\intr'.hold';

4:

{In state 4 we have the bus.  We keep it until we no longer require it
(HOLD inactive) AND some other master wants it (CBR active).}

brq = 1,
hlda' = hold', int' = 1, master' = hold',
itrq = 0,

0 = \reset',

{HOLD=0, CBR=1: proceed to state 5 to release the bus.}

5 = reset'.hold'.\cbr',

{HOLD=0, CBR=0, INTR=1: proceed to state 1 to perform interrupt.}

1 = reset'.hold'.cbr'.\intr';

5:

{In state 5, we release the bus and wait for BGR to go away before
returning to the idle state.}

brq = 0,
hlda' = 1, int' = 1, master' = 1,
itrq = 0,

0 = \reset'+bgr';

1:

{In state 1 we have been granted the bus for an interrupt transfer.
Drive the bus lines (enabled by INT), proceed to the next state (3)
unconditionally to activate ITRQ.}

brq = 1,
int' = 0, hlda' = 1, master' = 0,
itrq = 0,

0 = \reset',
3 = reset';

3:

{In state 3 we wait until the slave (the CPU) acknowledges the interrupt
transfer.  Then we proceed to state 6, which is much like state 4 (keeping
the bus in case we need it), except interrupt transfers are not generated.}

brq = 1,
int' = 0, hlda' = 1, master' = 0,
itrq  = tac',

0 = \reset',
6 = reset'.\tac';

2:

{State 2 is the equivalent of the idle state (0), only interrupt transfers
are not attempted until INTR has gone away, when we return to state 0.}

brq  = \hold',
hlda'= 1, int' = 1, master' = 1,
itrq  = 0,

0 = \reset'+hold'.intr',
6 = reset'.\hold'.\bgr'.tac';

6:

{State 6 is the equivalent of state 4 except that INTR is ignored.
We proceed to state 7 when giving up the bus.}

brq = 1,
hlda' = hold', int' = 1, master' = hold',
itrq = 0,

0 = \reset',
7 = reset'.hold'.\cbr';

7:

{State 7 is the equivalent of state 5: we give up the bus and
proceed to state 2 when BGR disappears.}

brq = 0,
hlda' = 1, int' = 1, master' = 1,
itrq = 0,

0 = \reset',
2 = reset'.bgr';

{End: generate 8-bit output file}  .8