{LANCE 10MHz Ethernet interface }
{State Machine for bus acquisition and interrupt transfer}
{RWT 08/03/85}

6 {Inputs:}  reset' hold' intr' cbr' bgr' tac'
5 {Outputs:} brq trq hlda' int' master'
3 {State bits}

| In state 0:
| The bus is requested if the LANCE wants to DMA or to interrupt.
| A transition to state 1 is made if we have been given the bus and
| we don't want to DMA (i.e. we want to interrupt).
| Once the bus has been granted for DMA, we go to state 4.

| In state 4:
| BRQ is left asserted.  We stay in state 4 even if HOLD goes away,
| unless CBR comes along (->state 0) or INTR comes along (->state 1).

| In state 1 the interrupt values are driven onto the address and
| control bus, and a transition is made to state 3 (normally straight
| away, but conditional on the previous TAC having gone away).

| In state 3 TRQ is asserted for the interrupt transfer.
| Transition to state 2 is made when TAC arrives.

| State 2 is like state 0 except that the bus is requested only for
| DMA, not for interrupts.  We go back to state 0 when the LANCE's
| interrupt request has disappeared, thereby allowing the next edge
| to generate another interrupt cycle.
| Once the bus is granted fro DMA, we go to state 6 (which is to state 2
| as state 4 is to state 0).

| In state 6 we keep the bus until CBR comes along.

| Every state contains a path to state 0 should RESET come along.

0: {Normal state, interrupt armed}
  brq  = (\hold'+\intr').reset',            | BRQ  = HOLD+INTR
  hlda'= 1,|\(\hold'.\bgr'.tac'.reset'),       | HLDA = HOLD.BGR.\TAC
  int' = 1,|\(\intr'.\bgr'.tac'.hold'.reset'), | INT  = INTR.BGR.\TAC.\HOLD
  master' = 1,|\(\bgr'.reset'.tac'.(\hold'+\intr')),
  trq  = 0,
  1    = \intr'.\bgr'.tac'.hold'.reset',  | 1    = INTR.BGR.\TAC.\HOLD
  4    = \hold'.\bgr'.tac'.reset';        | 4    = HOLD.BGR.\TAC

4: {Bus held for DMA}
  brq  = \hold'+cbr',                     | BRQ  = HOLD+\CBR
  trq  = 0,
  hlda'= hold',                           | HLDA = HOLD
  int' = 1,
  master' = hold',
  0    = \cbr'.hold'+\reset';             | 0    = \HOLD.CBR

1: {Interrupt phase 1: drive all but TRQ}
  brq  = 1,
  trq  = 0,|tac',                            | TRQ = \TAC
  hlda'= 1,
  int' = 0,
  master' = 0,
  3    = tac'.reset',                     | 3   = \TAC
  0    = \reset';

3: {Interrupt phase 2: drive TRQ}
  brq  = 1,
  trq  = tac',                            | TRQ = \TAC
  hlda'= 1,
  int' = 0,|\tac',                           | INT = \TAC
  master' = 0,|\tac',
  2    = \tac'.reset',                    | 2   = TAC
  0    = \reset';

2: {Normal state, interrupt disarmed}
  brq  = \hold',                          | BRQ  = HOLD
  trq  = 0,
  hlda'= \(\hold'.\bgr'.tac'),            | HLDA = HOLD.BGR.\TAC
  int' = 1,
  master' = \(\hold'.\bgr'.tac'),
  6    = \hold'.\bgr'.tac'.reset',        | 6    = HOLD.BGR.\TAC
  0    = intr'.hold'+\reset';             | 0    = \INTR.\HOLD

6: {Bus held for DMA}
  brq  = \hold'+cbr',                     | BRQ  = HOLD+\CBR
  trq  = 0,
  hlda'= hold',                           | HLDA = HOLD
  int' = 1,
  master' = hold',
  2    = \cbr'.hold'.reset',              | 6    = \HOLD.CBR
  0    = \reset';

.8