/** boc15.12.h */ /** 30-01-98 REused bit 4 of PI_PROCPROPS for alternative call convention */ /** boc15.11.h */ /** 24-03-97 Added symbolic constants for procfmt_procprops */ /* EPC Imp to C Translation Release 4 Version Apr 95 */ #include "imptoc.h" /** boc15.9.inc */ /** 21-02-96 Increased the size of the regmasks for Pentium to allow for */ /** Beta registers and correct modelling of address interlock */ /** 22-10-95 Added extra privprops for POWER & INTEL(pds) */ /** boc15.8.inc*/ /** 26-06-95 Added some 88K m-c dependent privprops bits */ /** boc15..7.inc*/ /** 21-04-95 Added FRAME ADDR TAKEN to PI_privprops to overcome problem */ /** with StackSTaddrflag when procedures are nested. This flag */ /** is part ot the proc general info */ /** Also added DCALLS SELF to aid later detection of tail */ /** recursion */ /** boc15.6.inc*/ /** 03-02-95 Added RETURNS QUAD for 128 bit real support and ADDR FROM GOT */ /** for better scheduling of MIPs PIC code(pds) */ /** boc15..5.inc*/ /** 02-11-94 Added RETURNS LONG for 64 bit integer support */ /** boc15.4.inc*/ /** 20-10-94 Further flags and field for Pascal Global jumps on MIPs */ /** where the ABI causes immense problems */ /** boc15.3.inc*/ /** 06-09-94 Further private property flags for Pentium */ /** boc15.2.inc*/ /** 19-08-94 Extra fields and flags for PowerPC/RS6000 ABIs. (pds) */ /** boc15.1.inc*/ /** 28-07-94 Additional flags for RS6000/POWER with dual ABIs. (pds) */ /** boc15.inc*/ /** 09-05-94 Removed _archinfo field as they are now redundant. (rt) */ /** boc14.2.inc*/ /** 25-04-94 Changed FIRST OF PAIR and SECOND OF PAIR to */ /** BARRIER INSTR and STRONG BARRIER to implement */ /** more general ordering constraining for MIPS PIC. (rt) */ /** boc14.1.inc*/ /** 15-04-94 Made NON ANNUL INSTR a common private property. (rt) */ /** boc14.inc*/ /** 22-03-94 Removed unused _rettype field from SPARC ProcFmt. (rt) */ /** boc13.inc*/ /** 18-03-94 Added support for Pentium. (pds) */ /** boc12.inc*/ /** 21-02-94 Added CONST ACCESS and NON ANNUL INSTR private instruction */ /** properties. (rt) */ /** boc11.inc*/ /** 06-01-94 Removed _switchid field from fragfmt - switchid now stored */ /** in the switch descriptor itself. Also removed _adid field */ /** from instructions as it is not used. Defined a new object area */ /** AUXBSS. Removed HAS CODE fragment property as it is */ /** redundant. (rt) */ /** boc10.inc*/ /** 13-10-93 Added returnlab field to M88K Procfmt. Also added privprops */ /** field to M88K and SPARC Procfmt. Added branch prediction */ /** flags. Also added flags for instruction pairing. Added */ /** procnum field to ProcFmt. Renamed POINTER DOMAIN TO ACCESS DOMAIN*/ /** and inverted meaning. (rt) */ /** boc9.inc*/ /** 03-09-93 Divided RETURNS REAL flag into RETURNS SREAL and */ /** RETURNS DREAL. Added POINTER DOMAIN instruction private */ /** property. Separated area and domain in instruction records - */ /** we can know have a fixup instruction which loads a pointer to */ /** a particular domain. (rt) */ /** boc8.inc*/ /** 26-07-93 Added NO SPEC EXEC instruction property. (rt) */ /** boc7.inc*/ /** 25-07-93 Added extra flags for stack frame size. (rt) */ /** boc6.inc*/ /** 10-06-93 Merge of MIPS and SPARC versions for port of GIS to MIPS */ /** architecture. (rt) */ /*------------------------------ START OF MIPS CHANGES ------------------------*/ /** boc3.3.inc*/ /** 16-04-93 Added CXTnum to instr record for aliasing info. (pds) */ /** boc3.2.inc*/ /** 06-04-93 Added hiddenadjust into Procfmt for realigning */ /** parameters. (pds) */ /** boc3.1.inc*/ /** 10-11-92 MIPS added and further revisions to instr_props field */ /** to use the same bits as global scheduler. (pds) */ /** boc2.inc*/ /** 05-10-92 Some revisions to instrfmt_props constants and addition */ /** of consts for procfmt_privprops. (pds) */ /*------------------------------- END OF MIPS CHANGES -------------------------*/ /** boc5.inc*/ /** 15-01-93 Changed preddescfmt to hold a flag showing if the edge is */ /** associated with a dense switch table. (rt) */ /** 07-12-92 Various further changes for global scheduler interface. (rt) */ /** boc4.inc*/ /** 30-09-92 Changes from USL/EPC SPARC C compiler merged in prior to */ /** global scheduling development. (rt) */ /** boc3.inc*/ /** 29-09-92 Merge of latest VME and RS/6000 variants of this file prior to */ /** global scheduling development. (rt) */ /** */ /*---------------------------- START OF RS/6000 CHANGES ------------------------*/ /** boc2.inc*/ /** 29-09-92 Various changes to support RS/6000. (pds) */ /** */ /*----------------------------- END OF RS/6000 CHANGES -------------------------*/ /** */ /** boc1.6.inc*/ /** 22-04-92 Added LOCACC INSTR property for instructions that are validly */ /** referenced in the local access descriptor list associated with */ /** their parent fragment. If the instructions are modified then this*/ /** bit is reset. (rt) */ /** 08-04-92 Added EXTCALL FRAG fragment property for VMEPLI to mark which */ /** fragments make an external call. (rt) */ /** 30-03-92 Added FixedAreaROStat array which is non-zero for compiler areas*/ /** which are read-only. (rt) */ /** 30-03-92 Added preddescfmt for predecessor fragment lists. This format is*/ /** used in global register usage analysis. Also added archinfo field*/ /** to fragfmt to point at architecture specific info associated with*/ /** a particular fragment. Renamed SWITCH TABLE JUMP to DSWITCH JUMP*/ /** INSTR and changed delay slot properties flags to use 4 different*/ /** flags. DELAY SLOT EXISTS and DELAY SLOT UNUSED have the following*/ /** meaning: */ /** | EXISTS | UNUSED | IMPLICATION */ /** FALSE FALSE Instruction may not have a delay slot */ /** FALSE TRUE Instruction may have a delay slot but it */ /** does not physically exist as yet */ /** TRUE FALSE Instruction is followed by a useful delay */ /** slot instruction. */ /** TRUE TRUE Instruction is followed by a delay slot */ /** instruction but it is only a NOP as yet */ /** Additionally, a delay slot instruction itself is marked with the*/ /** property DELAY SLOT INSTR. If DELAY SLOT EXISTS and DELAY SLOT */ /** UNUSED are both true then if SLOT COPIED is also true then */ /** the delay slot is set to hold a copy of the jump destination */ /** instruction when the code is actually generated. (rt) */ /** boc1.5.inc*/ /** 16-03-92 Added FRAGALLOCSIZE and INSTRALLOCSIZE plus various constants */ /** related to lrecfmt to make the size of memory requests from the */ /** backend optimiser as close to powers of 2 as possible. This */ /** improves the memory allocation as an exponential buddy allocator*/ /** is now situated between the backend optimiser and the system */ /** dynamic memory handling routines. (rt) */ /** 14-03-92 Added a GLA EXCUR INSTR enumeration to the instruction properties*/ /** field. This is set for instructions which use GLA base pointer */ /** to point to other than the GLA base. (rt) */ /** 09-03-92 Changed FixedAreaNames to give the same names to the areas as */ /** the corresponding enumeration. (rt) */ /** boc1.4.inc*/ /** 19-02-92 Additions to support redundant local store elimination. The */ /** fragfmt record has been expanded to incorporate information */ /** required for the dataflow analysis necessary to determine memory*/ /** access liveness. For each fragment, the analysis generates a */ /** locacc record list which details each instruction in the fragment*/ /** which may access the locals on the stack frame. Also added a */ /** RETURN FRAG property for fragments which return and cannot fall */ /** through to their successor. Renamed DEAD MEMACC INSTR property */ /** to KILLER LOAD INSTR. Added a BLOCKMARK pseudo instruction to */ /** mark start of new blocks inside a function and blockid field */ /** in fragfmt to hold the number of the block to which the fragment*/ /** belongs. These changes are required for the redundant store */ /** analysis of functions containing nested blocks. (rt) */ /** */ /** 05-12-91 Added ENTRY ACS32 FRAG and REBALANCED FRAG as fragment */ /** properties. Added paramsize to Procfmt for VMEPLI. (rt) */ /** boc1.3.inc*/ /** 14-11-91 Added VP RB NOFF for access via register base with no offset. */ /** Renamed SPILL LOAD INSTR to DEAD MEMACC INSTR. Also added a */ /** DSWITCHNOTE group. Renamed fragbusy to fragsize in Procfmt. (rt)*/ /** */ /** boc1.2.inc*/ /** 31-10-91 Changed fragfmt records to prevent address and final fields from*/ /** being aliased. (rt) */ /** */ /** boc1.1.inc*/ /** 21-10-91 Removed the group LABEL ADDR. Renamed EXTEN INSTR FORM to */ /** INSTR 32BIT. Renamed SWITCH CASE FRAG to DSWITCH CASE FRAG. */ /** Renamed SWITCH TABLE FRAG to DSWITCH JUMP FRAG. */ /** */ /** Added in, out, def and ref fields to fragfmt record for live */ /** register analysis. */ /** */ /** Add VP ANNULLED as a variant property. This is used for jump */ /** instructions where the delay slot instruction is annulled if the*/ /** jump is not taken. */ /** */ /** Added a new instruction property SPILL LOAD INSTR to mark */ /** loads which access a temporary location used for register spills.*/ /** After such a marked load the location must be dead. */ /** */ /** Added SETACS32 as an instruction property. This is set by all */ /** instructions in VMEPLI which set the ACC size to 32 bits. (rt) */ /** */ /** boc1.inc*/ /** 25-09-91 This is a new include file designed to hold all constants and */ /** record formats applicable to the backend optimiser (bprocs) */ /** module. This optimiser is designed to be common across all */ /** architectures (including non-Emachine 4 such as VME). The */ /** constants in this module were obtained by splitting the cgc32.inc*/ /** include file. The _ref and _def fields in the instruction formats*/ /** for SPARC and M88K have been removed as they are redundant. (rt)*/ /** */ /************************************************************************* */ /* * */ /* Constant definitions common to all back end optimisers * */ /* * */ /************************************************************************* */ /** */ /** */ /** Compiler object areas */ #define STACK 0 /* current stack frame and statically enclosing stack */ /* frames accessable via display */ #define CODE 1 /* generated code - no explicit references to this */ /* area may be made by the compiler */ #define GLA 2 /* directly addressable area which may contain fixups */ #define PLT 3 /* code generator area for read-only linkage and */ /* for storing constants */ #define SST 4 /* holds constant arrays only accessable via fixups */ /* in GLA or PLT */ #define UST 5 /* holds static arrays and character data */ #define DIAGS 6 /* diagnostic data accessable via fixups in GLA */ #define PARAMS 7 /* parameter passing area allowing for different */ /* architectural conventions */ #define IOTAB 8 /* primarily used for FORTRAN I/O control tables */ #define ZUST 9 /* data area zeroed at load time (also called BSS) */ #define CNST 10 /* code generator area for storing constants */ #define AUXBSS 11 /* auxiliary area zeroed at load time */ #define MAXCOMPILERAREA 11 /** */ /** Names of compiler areas for tracing purposes */ #if(Language==CCOMP) static char * FixedAreaNames [MAXCOMPILERAREA+1] = { "LOCALS", "CODE","__EPC_data","_GLOBAL_OFFSET_TABLE_","SST","UST","DIAGS","PARAMS", "IOTAB","ZUST","CNST","AUXBSS" }; #else static char * FixedAreaNames [MAXCOMPILERAREA+1] = { "Locals", "Code","Static","Plt", "Ust","Gst","Diags","Params", "IOarea","Bss","Consts","AuxBss" }; #endif; /** */ /** Compiler areas which may only be read at runtime */ static const int FixedAreaROStat [MAXCOMPILERAREA+1] = { 0, 1,0,1,1,0,1,0, 0,0,1,0}; /** */ /** */ /** Compiling context types */ /** */ #define CXTnoalias (1<<0) /*in this context loads and stores are */ /*guaranteed not to interfere */ #define CXTnoreuse (1<<1) /*in this context general fp operands are not */ /*going to be reused */ #define CXToverlap (1<<2) /*in this context loads and stores from */ /*adjacent instances of an unrolled can be */ /*intermingled */ /** */ /** Constants for traversing instruction chains */ /** */ #define NEXTCHAIN 1 #define PREVCHAIN 2 /** */ /** */ /** The approximate maximum number of instructions in a fragment before it is*/ /** broken automatically (without a label). This is to ensure that the */ /** schedulers do not have to cope with inordinately long fragments. */ /** */ #define MAXFRAGMENTSIZE 150 /** */ /** Enumeration of different types of dynamic memory areas used by backend */ /** */ #define MAGISARENA 0 #define MAGISDATA 1 #define MAGISSCOREBOARD 2 #define MAINSTRS 3 #define MAFRAGS 4 #define MAPREDDESCS 5 #define MASCHDESCRIPTORS 6 #define MAFIXUPCACHE 7 #define MALABADADAREA 8 #define MASWRECADAREA 9 #define MADENSESWITCHTABLE 10 #define MASPARSESWITCHTABLE 11 #define MAEXTERNALNAMEAREA 12 #define MAEXRECADAREA 13 #define MALABELS 14 #define MACODEHANDLEAREA 15 #define MAAREAKEYS 16 #define MALINEPREFIXES 17 #define MACONSTCACHEAREA 18 #define MAMAXNAMEDAREA 18 static char * MemoryAreaNames [MAMAXNAMEDAREA+1] = { "GIS_ARENA", "GIS_DATA","GIS_SCOREBOARD","INSTRS", "FRAGS","PRED_DESCS","SCH_DESCRIPTORS","FIXUP_CACHE", "LABADAD_AREA","SWRECAD_AREA","DENSE_SWITCH_TABLE", "SPARSE_SWITCH_TABLE", "EXTERNAL_NAME_AREA","EXRECAD_AREA","LABELS","CODE_HANDLE_AREA", "AREA_KEYS","LINE_PREFIXES","CONST_CACHE_AREA"}; /** */ /** Enumerated return values for the store access alias detection function */ /** */ #define MONO (-1) #define MOMAYBE 0 #define MOYES 1 #define MOEXACT 2 /** */ /** */ /** Pseudo instruction groups */ /** */ /** Psuedo instructions appear alongside real instructions in the code stream.*/ /** They must not contain information vital to final code generation or be */ /** associated with a particular adjacent real instructions since they may be*/ /** moved about or be deleted by the backend optimiser. */ /** */ #define MARKER 31 /*marker in code stream for subsequent ref */ #define LINENUMBER 32 /*marks start of a source line in code */ #define DBXINFO 33 /*holds debugging information for dbx */ #define CXTCHANGE 34 /*denotes a change of context */ #define DSWITCHNOTE 35 /*marks dense switch case with fragment */ /*of switch jump */ #define LINEDEBUG 36 /*holds debugging information associated */ /*with a particular source line */ #define DELETED 37 /*marks an instruction which has been */ /*deleted but not unchained from the */ /*instruction list */ #define REGIONINFO 38 /*holds information about region structure */ #define FIXUPPOINT 39 /*fix word to this place in code */ #define COPYASM 40 /*copy assembler text to code stream */ #define MINPSEUDOGROUP 31 /*minimum psuedo instruction group */ #define MAXPSEUDOGROUP 40 /*maximum allowed value in group field */ /** */ /** */ /** Constants for fragfmt props field */ /** */ #define FALLSTHROUGH (1<<0) /*control can flow to next seq frag */ #define FALLENINTO (1<<1) /*control can fall into this frag */ #define USERASSEMFRAG (1<<2) /*frag contains in-line assembler */ #define DSWITCHJUMPFRAG (1<<3) /*frag contains dense switch branch */ /*code */ #define DSWITCHCASEFRAG (1<<4) /*frag is potentially a destination */ /*fragment of a dense switch jump */ #define RETURNFRAG (1<<5) /*fragment returns - no fall thro' */ #define RETURNBRANCH (1<<6) /*fragment branches to epilogue */ #define NOCOALESCEHEAD (1<<7) /*frag should not be head of coalesce*/ #define NOCOALESCETAIL (1<<8) /*frag should not be tail of coalesce*/ #define NODELETEFRAG (1<<9) /*frag should not be deleted */ #define NOGISFRAG (1<<10) /*frag should not be globally sched */ #define NOOPTIMFRAG (1<<11) /*frag should not be optimised */ #define PRIVATELABFRAG (1<<12) /*frag inflow ignored by backend */ /*optimiser predecessor frag list */ #define GLOBALLABFRAG (1<<13) /* frag may be entered by glob jump or */ /* C++ exception. Frag cant be resued */ #define COMMONTAIL (1<<14) /* A common tail frag */ /** Constants for instrfmt props field */ /** (these are used by GIS and should not be changed without modifying the */ /** GIS functional interface definition) */ #define COPYINSTR (1<<0) /*instruction is a register copy */ #define DELAYSLOTEXISTS (1<<1) /*instruction has a delay slot */ #define DELAYSLOTUNUSED (1<<2) /*instr's potential delay slot is */ /*not yet used. If DELAY SLOT EXISTS */ /*is true then it is a NOP instr. */ #define DSMUSTEXIST (1<<3) /*delay slot instruction must exist */ #define DELAYSLOTINSTR (1<<4) /*instruction is in a delay slot */ #define ANNULLED (1<<5) /*instr is branch whose delay slot */ /*is to be annulled */ #define ANNULLEDTAKEN (1<<6) /*delay slot annulled if branch taken*/ #define BRANCH (1<<7) /*instr is a branch to a label */ #define CONDITIONALBRANCH (1<<8) /*instr is a conditional branch instr*/ #define JUMPINSTR (1<<9) /*instr is a branch to unknown dest */ #define ANYCALL (1<<10) /*instr is any sort of call */ #define UNKNOWNFLOW (1<<11) /*instr is call with unknown control */ #define LOADINSTR (1<<12) /*any load-from-memory instruction */ #define STOREINSTR (1<<13) /*any store-to-memory instruction */ #define DESTROYABLE (1<<14) /*instr may be moved/deleted by GIS */ #define FRAMEMODIFY (1<<15) /*instr modifies size of stack frame */ #define WRAPPERINSTR (1<<16) /*instr saves or restores callee regs*/ #define NONDSCAND (1<<17) /*instr cannot be put in a delay slot*/ #define NOSPECEXEC (1<<18) /*instr cannot be speculatively exec */ #define PREDICTED (1<<19) /*instr is a predicted branch */ #define PREDICTEDTAKEN (1<<20) /*instr is a predicted taken branch */ #define BARRIERINSTR (1<<21) /*instr is order constraint barrier */ #define STRONGBARRIER (1<<22) /*instr is strong constraint barrier */ #define POTENDOUBLEINSTR (1<<23) /*instr may require two issue slots */ #define KILLERLOADINSTR (1<<24) /*last access to stack location */ #define NOGISDSFILL (1<<25) /*delay slot not to be filled by GIS */ /** Constants for instr_privprops (architecture independent) */ #define FRAMEACCESS (1<<0) /*access stack frame so need adjustment*/ #define OVERLONG (1<<1) /*jump cannot reach */ #define NOINTERFERENCE (1<<2) /*memory refs do not interfere */ #define ADJACENTLOOPS (1<<3) /*as NO INTERFERENCE but in loops */ #define SLOTCOPIED (1<<4) /*destination instr in delay slot */ #define REGVARASSN (1<<5) /*assignment to register variable */ /*precludes some peephole optimisations*/ #define FIXEDINSTR (1<<6) /*will be fixed up at load */ #define VOLATILELOC (1<<7) /*access location is volatile */ #define PROCADFIX (1<<8) /*fix to procid not area and offset */ #define DISPLAYSETUP (1<<9) /*part of display setup - deletable */ #define KNOWNOFFSET (1<<10) /*jump to fixed displacement not label */ #define SYMBOLICACCESS (1<<11) /*assembler output only - symbolic in */ /*case it is in short data */ #define PARTACCESS (1<<12) /*part of misaligned access to data */ #define MULTIPLYINDIRECT (1<<13) /*load/store which is multiply indirect*/ #define SLOWRESULTINSTR (1<<14) /*results of instr take more than one */ /*cycle to be generated */ #define SCHRESTRICTINSTR (1<<15) /*indicates basic block scheduler */ /*cannot move instructions over this */ #define DSWITCHJUMPINSTR (1<<16) /*dense switch jump instruction */ #define DIRECTCALL (1<<17) /*call to a particular function */ #define GOTREDTAPE (1<<18) /*instr needed to set up or save and */ /*restore GOT register */ #define CONSTACCESS (1<<19) /*access to constant data - not aliased*/ #define NONANNULINSTR (1<<20) /*instruction cannot be annulled */ /** Constants for instr_privprops (architecture dependent) */ #if(Target==SPARC) #define FLOATWRAPPER (0x80000000) /*instr saves/restores float reg */ #else #if(Target==M88K) #define PADDINGINSTR (1<<30) /*pad instr to force label align */ #define CMPGENCONDITION (0x80000000) /*condition gen from cmp instr */ #define LASTPROLOGUEINSTR (0x20000000) /* Last instr in entry prologue */ #define FIRSTEPILOGUEINSTR (0x10000000) /* Fisrt instr in exity Epilogue */ #else #if(Target==VMEPLI) #define INSTR32BIT (1<<27) /*instruction is 32 bits in length */ /*instead of 16 bits */ #define SETACS32INSTR (1<<28) /*instr sets ACC size to 32 bits */ #define GLAEXCURINSTR (1<<29) /*GLAREG does not hold GLA base for */ /*this instruction */ #define GLARELOADINSTR (1<<30) /*instruction reloads the GLAREG */ /*after an excursion where it */ /*points elsewhere */ #define EXTENINSTRFORM (0x80000000) /*instr should use longest form */ /*available since it is fixed up */ #else #if(Target==MIPS) #define ADDRFROMGOT (1<<29) /* Loading address from GOT */ #define SIMPLEHAZARD (1<<30) /*needs a nop after it */ #define COMPLEXHAZARD 0x80000000 /*needs more than one nop after it */ #else #if(Target==PENTIUM) #define DEADREGUTIL (1<<24) /*Utilises dead reg in loop */ #define BYTEREGOP (1<<25) /*Uses the byte regs AL,AH etc */ #define PRECISIONREDN (1<<26) /*St-ld only to reduce preision */ #define PARAMRECLAIM (1<<27) /*Reclaiming parameter stack space */ #define EXTENINSTRFORM (1<<28) /*instr has special long form */ #define SIBREQD (1<<29) /*SIB needed for store access */ #define FIXEDLIT (1<<30) /*literal to be fixed up */ #define DSWITCHLOADINSTR 0x80000000 /*access to switch table location */ #else #if(Target==RS6) #define INPUTPARAMCOPY (0x80000000) /* Copy from oflow area to main area*/ #define INPUTPARAMSTORE (1<<30) /* Store of register Param */ #define PARAMSPILLINSTR (1<<29) /* Spill/reload when param passing */ #define WRAPPERINCR (1<<28) /* Offsets increase if wrappers increase */ #define WRAPPERDECR (1<<27) /* Offsets decrease if wrappers decrease */ #endif #endif #endif #endif #endif #endif; /** Constants for procedure properties (procfmt_procprops) */ #define PP_EXTERNAL (1<<0) /* proc is externally visible */ #define PP_MAINENTRY (1<<1) /* this is main or equivalent */ #define PP_NODISPLAY (1<<2) /* proc does not need a display */ #define PP_NOLOCALS (1<<3) /* proc has no local variables */ #define PP_ALTCALLCONV (1<<4) /* now obsolete */ #define PP_NOINTERNAL (1<<5) /* no internal blocks or procedures */ #define PP_SETUNASS (1<<6) /* fill stack frame with unassinged */ #define PP_HASSIDEE (1<<7) /* Proc has one or more side entries */ /* For C++ read catch blocks for entries*/ #define PP_PRIVATE (1<<8) /* Must be zero */ #define PP_RETURNSAG (1<<9) /* Proc returns aggreagte via 'hidden' */ /* parameter */ #define PP_NOALIAS (1<<10) /* proc has no pointers to local frame */ #define PP_INITPROC (1<<11) /* Call this proc from .init sen */ #define PP_FINIPROC (1<<12) /* Call this proc from .fini section */ #define PP_UNKNWNFLOW (1<<13) /* Proc has unknown control flow */ #define PP_NOTRETURN (1<<14) /* proc does not return */ #define PP_BUFFHNDLR (1<<15) /* proc is a buffer handler */ /* ie rarely called & no side effects */ /** */ /** Constants for procedure private properties (procfmt_privprops) */ /** */ #define RETURNSINT (1<<0) /*routine returns an integer result */ #define RETURNSSREAL (1<<1) /*routine returns a 32 bit real result */ #define RETURNSDREAL (1<<2) /*routine returns a 64 bit real result */ #define RETURNSCOMPLEX (1<<3) /*routine returns a complex result */ #define NOTLEAFRT (1<<4) /*routine contains calls to other routines*/ #define NESTEDCALLS (1<<5) /*call found when planting parameters */ #define NONVIRTUALFP (1<<6) /*real frame pntr needed e.g. alloca call */ #define NOREGEXPAN (1<<7) /*do not allow GIS to expand register use */ #define CALLSINTERNAL (1<<8) /*calls internal proc so display needed */ #define GLOBALACCESS (1<<9) /*makes data accesses via the display */ #define ACCESSEDGLOBAL (1<<10) /* My frame accessed form inner procs */ #define PARAMSACCESSEDGLOBALY (1<<11) /* My parameters ditto */ #define VARARGSPROC (1<<12) /* I have variable nos of params */ #define PARAMSSPILLED (1<<13) /* I have to spill & reload parameters */ /* while calling a callee proc */ #define SREALEQ (1<<14) /*compares short reals for equality */ #define GJUMPEDINTO (1<<15) /* Pascal may jump from inner proc back */ /* into this proc twisting the stack */ #define RETURNSLONG (1<<16) /* routine returns a 64 bit integer result*/ #define RETURNSQUAD (1<<17) /* routine returns a 128 bit real result */ #define FRAMEADDRTAKEN (1<<18) /* routine takes the address of a */ /* non temporay in its stack frame */ #define DCALLSSELF (1<<19) /* Proc has a direct recursive call */ /* Indirec recursion is not detected */ /** Properties for region structure information in REGIONINFO psuedo instr */ #define RPINCELLAR (1<<0) /*represents a cellar region */ #define RPGISRESTRICTED (1<<1) /*represents a GIS restricted region */ #define RPTOPLEVEL (1<<2) /*represents the top level region */ #define RPCONTAINER (1<<3) /*represents a container region */ #define RPBBSCHEDULED (1<<4) /*represents a basic block sched region */ #define RPUNROLLED (1<<5) /*represents an unrolled region */ #define RPSTART (1<<6) /*represents the start of a region */ /** */ /** Special constants for GIS bubble information in bubbles field */ /** */ #define BIBUBBLES 250 /*represents unknown bubbles before issue */ #define BIITOPT 251 /*represents IF-THEN delay slot optimisation */ #define BIITEOPT 252 /*represents IF-THEN-ELSE delay slot optim */ #define BIUNCONDOPT 253 /*represents uncond branch delay slot optim */ #define BIOVEROPT 254 /*represents branch over delay slot optim */ #define BIPOSTFILL 255 /*represents delay slot post fill optimisation*/ /** Constants for GIS issue information in instruction issueprops field */ /** Common Properties */ #define TPGLOBSCHED (1<<0) /*instr has been globally scheduled */ #define TPIGSTART (1<<1) /*instr is first in issue group */ #define TPQUEUED (1<<2) /*instr queues for the exec unit */ #define TPCASCADED (1<<3) /*instr uses cascade results */ #define TPCOPYBYPASS (1<<4) /*instr uses bypassed reg contents */ #define TPISCONTROL (1<<5) /*instr is of a control type */ /** Control instruction properties */ #define TPCONFLUENCE (1<<6) /*instr is branch to confl label */ #define TPPREDICTED (1<<7) /*instr is a predicted branch */ #define TPPREDICTEDTAKEN (1<<8) /*instr is predicted taken branch */ #define TPIFTHEN (1<<9) /*instr is conditional of if/then */ #define TPIFTHENELSE (1<<10) /*instr is cond of if/then/else */ #define TPITECOLLAPSE (1<<11) /*instr is collapsed if/then/else */ #define TPLOOPBRANCH (1<<12) /*instr is loop back edge branch */ /** */ /** Non-Control instruction properties */ #define TPGLUED (1<<6) /*instr has been glued */ #define TPREFRESH (1<<7) /*instr is loop hoist refresh load */ #define TPOPTACCESS (1<<8) /*instr is access to optimised loc */ #define TPMIGRATED (1<<9) /*instr has migrated from home block*/ #define TPCONTSPEC (1<<10) /*instr is executed control spec */ #define TPDATASPEC (1<<11) /*instr is executed data spec */ #define TPMEMSPEC (1<<12) /*instr is executed memory spec */ #define TPHOISTED (1<<13) /*instr has been hoisted out of loop*/ #define TPEARLY (1<<14) /*instr migrated over a call */ /************************************************************************* */ /** * */ /** RECORD FORMATS * */ /** * */ /************************************************************************* */ /** The predecessor descriptor format. The preds field of each fragment */ /** points to a linked list of these descriptors which gives the set of */ /** all fragments that control may enter that fragment by. Frag is a pointer */ /** to the fragment concerned and isforward is non-zero if the control edge */ /** represented by the descriptor is forward (i.e. the predecessor */ /** physically preceeds the concerned fragment). */ struct preddescfmt{ int frag; /*addr of edge source fragment */ int next; /*next preddesc in chain */ int allocchain; /*next allocated descriptor */ short int isforward; /*non-zero if a forward edge */ short int isswitchedge /*non-zero if a switch edge */; }; #define PREDDESCFMTSIZE 16 #define PREDDESCALLOCSIZE 256 #if(Target==SPARC) /** Definition of instruction record. These records hold information about */ /** individual instructions, both real executable instructions and pseudo */ /** instructions planted in the code stream. */ struct instrfmt{ struct instrfmt* previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code */ unsigned char opcode; /*internal representation */ unsigned char variant; /*gives operand addressing mode */ unsigned char datasize; /*in bytes */ unsigned char CXTnum; /*context identifier for aliasing */ unsigned char rd; /*destination reg (usually) */ unsigned char rs1; /*first source reg */ unsigned char rs2; /*second source reg */ unsigned char bubbles; /*pipeline bubbles before execution */ short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int issueprops; /*GIS issue trace information */ union { int offset; /*if known, else -1 */ int parregs; /*call parameter registers used */ int CXTset; /*bitmap of contexts to be set */ } u0; union { int immval; /*immediate value */ int CXTunset; /*bit mask of def integer regs */ struct instrfmt *linkedinstr; /* link to associated instr */ } u1; int props; /*public instr property flags */ int privprops; /*private instr property flags */ int rref; /*bit mask of ref integer regs */ int rdef; /*bit mask of ref integer regs */ int fref; /*bit mask of ref float regs */ int fdef; /*bit mask of def float regs */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 60 #define INSTRALLOCSIZE 136 /** Definition of fragment record. Fragments hold lists of instructions */ /** delineated into basic blocks. */ struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of associated switch table*/ int preds; /*list of fragment predecessors */ int rin; /*int regs live on fragment entry */ int fin; /*float regs live on fragment entry */ int rout; /*int regs live on fragment exit */ int fout; /*float regs live on fragment exit */ int rdef; /*int regs defined by the fragment */ int fdef; /*float regs defined by the fragment*/ int ruse; /*int regs used by the fragment */ int fuse; /*float regs used by the fragment */ int address; /*code area offset, after optimising*/ int archinfo; /*pointer to architecture specific*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 96 #define FRAGALLOCSIZE 85 /** Definition of a Procedure record. This record holds information relating */ /** to a particular procedure for which code has been generated. */ struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ struct instrfmt *callinstr; /*address of NOP after last call */ struct instrfmt *setdiag; /*marker for F77 diag offset */ int labadjust; /*the label fix for this proc */ int procprops; /*as passed to Mstartproc */ struct instrfmt *framemark; /*marker of stack-build instr */ int auxstacklab; /*label of EAUXADD error code */ int returnlab; /*returns done by jump to end */ int markerad; /*stack disp to IDIA, FDIA, etc */ int proclevel; /*nesting level of this proc */ int rref; /*general regs referenced in proc */ int rdef; /*general regs defined in proc */ int fref; /*float regs referenced in proc */ int fdef; /*float regs defined in proc */ struct instrfmt *unassignmark; /*marker for stack-fill count */ int privprops; /*private flags for generator */ int inparsize; /*size of incoming parameter area */ int outparsize; /*size of outgoing parameter area */ int saveareasize; /*size allowed for reg save area */ int localsize; /*size of frame for local storage */ int ffsize; /*the fixed frame size - the reg */ /*save and out parameter area */ int framesize; /*size of stack frame */ int lowreg; /*index of 1st non-param register */ }; #endif; #if(Target==M88K) struct instrfmt{ struct instrfmt * previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code */ unsigned char opcode; /*internal representation */ unsigned char variant; /*gives operand addressing mode */ unsigned char datasize; /*in bytes */ unsigned char CXTnum; /*context identifier for aliasing */ unsigned char rd; /*destination reg (usually) */ unsigned char rs1; /*first source reg */ unsigned char rs2; /*second source reg */ unsigned char bubbles; /*pipeline bubbles before execution */ short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int issueprops; /*GIS issue trace information */ union { int offset; /*if known, else -1 */ int parregs; /*call parameterregisters used */ int CXTset; /*bitmap of contexts to be set */ } u0; union { int immval; /*immediate value */ int CXTunset; /*bitmap of contexts to be unset */ struct instrfmt *linkedinstr; /* link to associated instr */ } u1; int props; /*public instr property flags */ int privprops; /*private instr property flags */ int rref; /*bit mask of ref general regs */ int rdef; /*bit mask of def general regs */ int fref; /*bit mask of ref extended regs */ int fdef; /*bit mask of def extended regs */ int chain; /*general instruction chain field */ int stackadj; /*relocation required for access */ /*via STACKPOINTER */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 68 #define INSTRALLOCSIZE 120 struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of associated switch table*/ int preds; /*list of fragment predecessors */ int rin; /*int regs live on fragment entry */ int fin; /*float regs live on fragment entry */ int rout; /*int regs live on fragment exit */ int fout; /*float regs live on fragment exit */ int rdef; /*int regs defined by the fragment */ int fdef; /*float regs defined by the fragment*/ int ruse; /*int regs used by the fragment */ int fuse; /*float regs used by the fragment */ int address; /*code area offset, after optimising*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int archinfo; /*pointer to architecture specific */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 96 #define FRAGALLOCSIZE 85 struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ struct instrfmt *setdiag; /*marker for F77 diag offset */ int labadjust; /*the label fix for this proc */ int procprops; /*as passed to Mstartproc */ struct instrfmt *framemark; /*marker of stack-build instr */ int auxstacklab; /*label of EAUXADD error code */ int returnlab; /*returns done by jump to end */ int markerad; /*stack disp to IDIA, FDIA, etc */ int proclevel; /*nesting level of this proc */ int returnmark; /*marker of stack-collapse instr */ int rref; /*general regs referenced in proc */ int rdef; /*general regs defined in proc */ int fref; /*float regs referenced in proc */ int fdef; /*float regs defined in proc */ int entryregs; /*mask of regs live at proc entry */ int entryxregs; /*mask of fregs live at proc entry */ int entrypairs; /*mask of reg pairs live on entry */ int privprops; /*private flags for generator */ int inparsize; /*size of incoming parameter area */ int outparsize; /*size of outgoing parameter area */ int saveareasize; /*size allowed for reg save area */ int localsize; /*size of frame for local storage */ int ffsize; /*the fixed frame size - the reg */ /*save and out parameter area */ int framesize; /*size of stack frame */ int rsave [63+1]; /*stack offsets of reg save words */ }; #endif; #if(Target==RS6) struct instrfmt{ struct instrfmt * previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code */ unsigned char variant; /*gives operand addressing mode */ unsigned char datasize; /*in bytes */ unsigned char CXTnum; /*context identifier for aliasing */ unsigned char rd; /*destination reg (usually) */ unsigned char rs1; unsigned char rs2; unsigned char rs3; /*source registers */ unsigned char bubbles; /*pipeline bubbles before execution */ short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int opcode; /*internal representation */ short int issueprops; /*GIS issue trace information */ union { int offset; /*if known, else -1 */ int parregs; /*call parameter registers used */ int CXTset; /*bitmap of contexts to be set */ } u0; union { int immval; /*immediate value */ int CXTunset; /*bitmap of contexts to be unset */ struct instrfmt *linkedinstr; /* link to associated instr */ } u1; int props; /*public instr property flags */ int privprops; /*private instr property flags */ int rref; /*bit mask of ref integer regs */ int rdef; /*bit mask of def integer regs */ int fref; /*bit mask of ref float regs */ int fdef; /*bit mask of def float regs */ int cref; /*bit mask of ref control regs */ int cdef; /*bit mask of def control regs */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 72 #define INSTRALLOCSIZE 113 struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of associated switch table*/ int preds; /*list of fragment predecessors */ int rin; /*int regs live on fragment entry */ int fin; /*float regs live on fragment entry */ int cin; /*control regs live on frag entry */ int rout; /*int regs live on fragment exit */ int fout; /*float regs live on fragment exit */ int cout; /*control regs live on fragment exit*/ int rdef; /*int regs defined by the fragment */ int fdef; /*float regs defined by the fragment*/ int cdef; /*control regs defined by the frag */ int ruse; /*int regs used by the fragment */ int fuse; /*float regs used by the fragment */ int cuse; /*control regs used by the fragment */ int address; /*code area offset, after optimising*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int archinfo; /*pointer to architecture specific */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 112 #define FRAGALLOCSIZE 73 struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ struct instrfmt *setdiag; /*marker for F77 diag offset */ int labadjust; /*the label fix for this proc */ int procprops; /*as passed to Mstartproc */ struct instrfmt *framemark; /*marker of stack-build instr */ int auxstacklab; /*label of EAUXADD error code */ int markerad; /*stack disp to IDIA, FDIA, etc */ int proclevel; /*nesting level of this proc */ struct instrfmt *unassignmark; /*marker for stack-fill count */ int swmark; /*to recover switch table space */ int labmark; /*to recover label table space */ int returnlab; /*returns done by jump to end */ int rref; /*general regs referenced in proc */ int rdef; /*general regs defined in proc */ int fref; /*float regs referenced in proc */ int fdef; /*float regs defined in proc */ int cref; /*control regs referenced in proc */ int cdef; /*control regs defined in proc */ int TBTbits; /*param flags for IBM traceback */ int privprops; /*private flags for generator */ int inparsize; /*size of incoming parameter area */ int outparsize; /*size of outgoing parameter area */ int saveareasize; /*size allowed for reg save area */ int localsize; /*size of frame for local storage */ int ffsize; /*the fixed frame size - the reg */ /*save and out parameter area */ int framesize; /*total size of stack frame */ int pseudoparams; /* offset of regenrated param area */ int pcaaddress; /* Area holding key to above area */ short int ipcnt; short int fpcnt; /*int and fp params for generator */ }; #endif; #if(Target==PENTIUM) /** values for intruction variant field on PENTIUM */ #define OPONLY 1 /* All data in opcode */ #define OPPLUSR 2 /* Only register is added to opcode */ #define OPR 3 /* Single register only (reg form of opmem) */ #define OPRR 4 /* Two regs form ie r-m and reg fields regs */ #define OPRRM 5 /* Register+store r-m field gives base&off */ #define OPRSLIT 6 /* Reg and 8-bit lit if r-m it has subopc */ #define OPRLIT 7 /* As above but lit MAY need 32 bits */ #define OPMEM 8 /* Unary op to mem r-m is mem reg subopcode */ #define OPRMR 9 /* As oprrm but to store not to reg */ #define OPEAXLIT 10 /* As oprlit but eax implied and r-m omm */ #define OPMEMLIT 11 /* Direct operation literal and memory */ #define OPPLUSRLIT 12 /* as Opplusr but lit field follows */ #define OPPCREL 13 /* Literal dispacememnt rel to pc */ #define FOPONLY 14 /* As oponly but floating op */ #define FOPPLUSR 15 /* As opplusr but r is float tos offset */ #define FOPRM 16 /* As oprm but tos is implied */ /* The next are 8086 hangovers and are */ /* rarely useful in 32 bit mode */ #define OPBRMLIT 17 /* Op on byte witj 8bit literal */ #define OPALLIT 18 /* Op directly on btm byte of eax */ #define OPBMEMLIT 19 /* Direct operation literal and memory byte */ #define MAXp5VARIANT 19 struct instrfmt{ struct instrfmt * previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code */ unsigned char opcode; /*internal representation */ unsigned char datasize; /*in bytes */ unsigned char CXTnum; /*context identifier for aliasing */ unsigned char rd; /*destination reg (usually) */ unsigned char rs1; /*first source reg */ unsigned char rs2; /*second source reg */ unsigned char bubbles; /*pipeline bubbles before execution */ int variant; /*details of how instruction built */ int disp; /*non-immval displacement */ short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int issueprops; /*GIS issue trace information */ unsigned char csize; /*instruction size in bytes */ unsigned char fixtype; /*type of fix up to be applied */ union { int offset; /*if known, else -1 */ int parregs; /*call parameter registers used */ int CXTset; /*bitmap of contexts to be set */ } u0; union { int immval; /*immediate value */ int CXTunset; /*bitmap of contexts to be unset */ struct instrfmt *linkedinstr; /* link to associated instr */ } u1; int props; /*public instr property flags */ int privprops; /*private instr property flags */ union { int prefixed; /*details of any prefixes */ unsigned char prefixes [3+1]; } u2; unsigned short rref; /*bit mask of def integer regs */ unsigned short rdef; /*bit mask of def integer regs */ unsigned short fref; /*bit mask of ref float regs */ unsigned short fdef; /*bit mask of def float regs */ unsigned short cref; /*bit mask of ref control regs */ unsigned short cdef; /*bit mask of def control regs */ unsigned char rmbyte; /*value of rm byte when relevant */ unsigned char sib; /*value of sib byte when relevant */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 73 #define INSTRALLOCSIZE 113 struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of switch table assoc frag*/ int preds; /*list of fragment predecessors */ unsigned short rin; /*int regs live on fragment entry */ unsigned short fin; /*float regs live on fragment entry */ unsigned short cin; /*control regs live on frag entry */ unsigned short rout; /*int regs live on fragment exit */ unsigned short fout; /*float regs live on fragment exit */ unsigned short cout; /*control regs live on fragment exit*/ unsigned short rdef; /*int regs defined by the fragment */ unsigned short fdef; /*float regs defined by the fragment*/ unsigned short cdef; /*control regs defined by the frag */ unsigned short ruse; /*int regs used by the fragment */ unsigned short fuse; /*float regs used by the fragment */ unsigned short cuse; /*control regs used by the fragment */ int address; /*code area offset, after optimising*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int archinfo; /*pointer to architecture specific */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 88 #define FRAGALLOCSIZE 93 struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ struct instrfmt *setdiag; /*marker for F77 diag offset */ int labadjust; /*the label fix for this proc */ int procprops; /*as passed to Mstartproc */ struct instrfmt *framemark; /*marker of stack-build instr */ int auxstacklab; /*label of EAUXADD error code */ int markerad; /*stack disp to IDIA, FDIA, etc */ int proclevel; /*nesting level of this proc */ struct instrfmt *unassignmark; /*marker for stack-fill count */ int swmark; /*to recover switch table space */ int labmark; /*to recover label table space */ int returnlab; /*returns done by jump to end */ int rref; /*general regs referenced in proc */ int rdef; /*generals regs defined in proc */ int fref; /*float regs referenced in proc */ int fdef; /*float regs defined in proc */ int cref; /*control regs referenced in proc */ int cdef; /*control regs defined in proc */ int IOsave; /*stack offset for IO result addr */ int privprops; /*private flags for generator */ int inparsize; /*size of incoming parameter area */ int saveareasize; /*size allowed for reg save area */ int localsize; /*size of frame for local storage */ int ffsize; /*the fixed frame size - the reg */ /*save and out parameter area */ int BEswopspace; /* Temp to unswop swopped reals */ int framesize; /*total size of stack frame */ short int ipcnt; short int fpcnt; /*int and fp params for generator */ }; #endif; #if(Target==VMEPLI) struct instrfmt{ struct instrfmt * previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code*/ unsigned char opcode; /*internal representation */ unsigned char variant; /*operand addressing mode */ unsigned char bubbles; /*pipeline bubbles before execution*/ unsigned char CXTnum; /*context identifier for aliasing */ union { char datasize; /*in bytes */ char maskval; /*used for conditional jumps */ } u0; short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int issueprops; /*GIS issue trace information */ union { int offset; /*if known, else -1 */ int parregs; /*call parameter registers used */ int extinfo; /*extra information for instr */ } u1; union { int immval; /*immediate value */ int labelid; /*label identifier for jumps */ } u2; int props; /*public instr property flags */ int privprops; /*private instr property flags */ int rref; /*bit mask of referenced regs */ int rdef; /*bit mask of defined regs */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 48 #define INSTRALLOCSIZE 170 struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of associated switch table*/ int preds; /*list of fragment predecessors */ int rin; /*regs live on fragment entry */ int rout; /*regs live on fragment exit */ int rdef; /*regs defined by the fragment */ int ruse; /*regs used by the fragment */ int address; /*code area offset, after optimising*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int archinfo; /*pointer to architecture specific */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 80 #define FRAGALLOCSIZE 102 struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ int rref; /*general regs referenced in proc */ int rdef; /*general regs defined in proc */ int inparsize; /*size of incoming parameter area */ }; #endif; #if(Target==MIPS) struct instrfmt{ struct instrfmt * previnstr; /*addr of previous instr record */ struct instrfmt * nextinstr; /*addr of next instr record */ unsigned char group; /*instr classification/special code */ unsigned char opcode; /*internal representation */ unsigned char datasize; /*in bytes */ unsigned char CXTnum; /*context identifier for aliasing */ unsigned char rd; /*destination reg (usually) */ unsigned char rs1; /*first source reg */ unsigned char rs2; /*second source reg */ unsigned char bubbles; /*pipeline bubbles before execution */ short int area; /*area if known, else -1 */ short int domain; /*domain if known, else 0 */ short int issueprops; /*GIS issue trace information */ union { int offset; /*if known, else -1 */ int parregs; /*call parameter registers used */ int CXTset; /*bitmap of contexts to be set */ } u0; union { int immval; /*immediate value */ int CXTunset; /*bitmap of contexts to be unset */ struct instrfmt *linkedinstr; /* link to associated instr */ } u1; int props; /*public instr property flags */ int privprops; /*private instr property flags */ int rref; /*bit mask of ref integer regs */ int rdef; /*bit mask of def integer regs */ int fref; /*bit mask of ref float regs */ int fdef; /*bit mask of def float regs */ int cref; /*bit mask of ref control regs */ int cdef; /*bit mask of def control regs */ int allocchain; /*next allocated instruction */ }; #define INSTRFMTSIZE 68 #define INSTRALLOCSIZE 120 struct fragfmt{ struct fragfmt * prevfrag; /*addr of previous fragment */ struct fragfmt * nextfrag; /*addr of next fragment */ int props; /*fragment properties vector */ int entryid; /*id of fragment external entry or */ /*0 if no entry (may be main entry */ /*point or a side entry) */ struct instrfmt * firstinstr; /*addr of first instruction record */ struct instrfmt * lastinstr; /*addr of last instruction record */ int labindex; /*if # 0 label number of entry label*/ int labref; /*if # 0 addr of label record */ /*accessed by terminating jump */ struct instrfmt * labrefinstr; /*instruction containing the labref */ int switchtab; /*address of associated switch table*/ int preds; /*list of fragment predecessors */ int rin; /*int regs live on fragment entry */ int fin; /*float regs live on fragment entry */ int cin; /*control regs live on frag entry */ int rout; /*int regs live on fragment exit */ int fout; /*float regs live on fragment exit */ int cout; /*control regs live on fragment exit*/ int rdef; /*int regs defined by the fragment */ int fdef; /*float regs defined by the fragment*/ int cdef; /*control regs defined by the frag */ int ruse; /*int regs used by the fragment */ int fuse; /*float regs used by the fragment */ int cuse; /*control regs used by the fragment */ int archinfo; /*pointer to architecture specific */ int address; /*code area offset, after optimising*/ struct fragfmt * final; /*actual dest of a ref to this frag */ int allocchain; /*pointer to next allocated fragment*/ int uses; /*frag use count when reorganising */ }; #define FRAGFMTSIZE 112 #define FRAGALLOCSIZE 73 struct procfmt{ struct fragfmt * procfrag; /*first frag for this proc */ struct fragfmt *cellarfrags; /*cellar fragments for this proc */ int procnum; /*the number of the procedure */ struct fragfmt *curfrag; /*the current frag */ int fragsize; /*approximate number of instrs */ struct instrfmt *setdiag; /*marker for F77 diag offset */ int labadjust; /*the label fix for this proc */ int procprops; /*as passed to Mstartproc */ struct instrfmt *framemark; /*marker of stack-build instr */ int auxstacklab; /*label of EAUXADD error code */ int markerad; /*stack disp to IDIA, FDIA, etc */ int proclevel; /*nesting level of this proc */ struct instrfmt *unassignmark; /*marker for stack-fill count */ int swmark; /*to recover switch table space */ int labmark; /*to recover label table space */ int returnlab; /*returns done by jump to end */ int rref; /*general regs referenced in proc */ int rdef; /*general regs defined in proc */ int fref; /*float regs referenced in proc */ int fdef; /*float regs defined in proc */ int cref; /*control regs referenced in proc */ int cdef; /*control regs defined in proc */ int GOTsave; /*stack offset for GOTaddr */ int SFAsave; /*stack offset for SFAaddr when */ /* unscrambling Pascal Global jumps*/ int hiddenadj; /*for realigning params */ int privprops; /*private flags for generator */ int inparsize; /*size of incoming parameter area */ int outparsize; /*size of outgoing parameter area */ int saveareasize; /*size allowed for reg save area */ int localsize; /*size of frame for local storage */ int ffsize; /*the fixed frame size - the reg */ /*save and out parameter area */ int framesize; /*total size of stack frame */ short int ipcnt; short int fpcnt; /*int and fp params for generator */ }; #endif; /** Definition of a label record */ struct lrecfmt{ int labnum; /*the label number */ struct fragfmt *frag; /*pointer to fragment holding */ /*the definition point of the */ /*label. This is 0 before the */ /*label is actually defined. */ struct fragfmt *freffrag; /*frag in which label is first */ /*referenced or defined */ int chain; /*next label in same bucket of */ }; /*the label hash table */ #define LRECBUCKETSIZE 1024 #define LRECBUCKETSHIFT 10 #define LRECSIZE 16 #define LRECSHIFT 4 /** Record format for basic block scheduler table information */ struct mschedulef{ unsigned char unit; /*the unit used by the instruction */ unsigned char blockage; /*number of beats the unit is blocked */ /*for (must be >0) */ unsigned char primlatency; /*primary latency for instr results */ /*(must be >0) */ unsigned char seclatency; /*secondary latency for instr results */ /*(those defined in alternatively */ /*delayed registers - must be >0) */ }; /***************************** end of boc.inc ************************************/