$l1m $44(Microprogrammed Hardware) $b2 $18(The Processor) $p1 The block diagram of the processor data path is shown below. It consists of 2 major sections, each of them built upon 3 16-bit busses: two for address and one for data. $b51 $l1m $22(Graphics processor - block diagram) $b1 $a indent=1 $item The left section has a general data processing capability. Its address busses: $32(lA[15:0]) and $32(lB[15:0]) support framestore's $22(X) and $22(Y) coordinate addresses. When concatenated, $32(lA[14:0]),$32(lB[15:0]) can be used to drive the APM system address bus $32(AD[31:1]). Only half-word accesses of system address space are possible. $b1 $item The right section is designed to support block moves of data and is capable of driving its address buses: $32(rA[15:0]) and $32(rB[15:0]) with consecutive values of one 32-bit address, or as two separate 16-bit counters. Right data and address lines support local memory with 8k bytes of ROM and 8k bytes of dual-ported RAM available locally on the processor board. The right data bus supports also APM system and framestore data transfers. $a indent=0 $b1 Data can be transferred between the left and right counterparts of the sections. $b2 $14(Left section) $p1 The major component of the left section is a 16-bit wide general-purpose data path, built out of 4 AM29203 4-bit "superslices". These are supported by a carry-lookahead circuit and an AM2904 status and shift control unit. Detailed functional descriptions of these units are provided in the appendix to this document. $p1 The AM29203 contains 16 16-bit dual-ported registers, where ports A and B can be output onto busses $32(lA[15:0]) and $32(lB[15:0]) for the values of microword fields $32{lAs}=0 and $32{lBs[1:0]}=00 respectively. Value 1 on $32{lAs} drives the bus $32(lA[15:0]) with the contents of the bus $32(rA[15:0]) and value 01 on $32{lBs[1:0]} drives $32(lB[15:0]) with $32(rB[15:0]). Value 10 on $32{lBs[1:0]} injects a 16-bit $32{constant[15:0]} microword field onto $32(lB[15:0]). $p1 The data bus $32(lD[15:0]) can be driven by the output from AM29203 alu shifter, for the field $32{ldatas[1:0]}=00. For $32{ldatas[1:0]}=01 left data bus picks up contents of its right counterpart: $32(Data[15:0]) and for 10, it contains swopped bytes of the bus $32(lA[15:0]): $32(lA[7:0]),$32(lA[15:8]). Control value 11 reads ($32[zero,carry,negative,overflow]) status bits from AM2904 onto $32(lD[3:0]). $p1 Microcode bits $32{shiftrl} and $32{spsi[7:0]} constitute instruction bits $32([8:0]) for the AM29203 slices. Bit $32{shiftrl} is also used as instruction bit $32{[10]}, controlling the direction of shift in the shift linkage section of the AM2904. $p1 Fields $32{rfmaA[3:0]} and $32{rfmaB[3:0]} provide register addresses for the AM29203 A and B register output ports. Field $32{rfmaB[4:0]} is also used to address registers during write operations. 16 bottom registers, addressed by 0,$32{rfmaB[3:0]} are the internal registers of the AM29203 and data is written into them from the bus $32(lD[15:0]). The top 16 addresses provide access to framestore control registers, for which the data has to be provided on $32(Data[15:0]). Addresses: 10000, 10001, 10010 and 10011 provide write access to colour, plane write enable, X display offset and Y display offset registers. $p1 Microword fields $32{AM04i[12:11]}, $32{shiftlk[3:0]} and $32{AM04i[5:0]} provide instruction bits $32([12:0]) for the AM2904. This device provides the $32[carryin] signal to the ALU of the AM29203 and all the necessary linkage for shifts. It supports the necessary status information and also generates a variety of condition signals for the sequencer. The detailed functional description of the device is provided in the appendix. Bits $32{AM04cemL} and $32{AM04ceuL}, when 0, enable the writes into the device's program and microprogram status registers. $p1 The AM2904 can generate on its condition output a variety of functions applied to the values of its 4 input lines and internal status bits. All the status information in the data path is fed into these inputs, and the multiplexing of the conditions onto 4 inputs lines is controlled by the microword bits: $32{condsel[7:6]}. For those bits being 00, inputs $32[(Iz,In,Ic,Iovr)] are connected to the ($32[zero, negative, carryout, overflow]) outputs from AM29203. 01 provides a vector ($32(dmaAdone,lD[4],dmaBdone,lD[7])), $32(dmaAdone) and $32(dmaBdone) being the completion signals from the right segment DMA modules. For 10 the testable vector is ($32(lD[0],lD[3],lD[2],lD[6])) and a 0 in a vector ($32(0,Yblank,lD[1],lD[5])), selected by 11 provides a constant for unconditional operations of the sequencer. $32[Yblank] when 1 indicates vertical blanking period in the framestore. $n $14(Right section) $p1 Address busses $32(rA[15:0]) and $32(rB[15:0]) of the right section can be driven from their designated DMA address generation units, or from their left counterparts. The selection is controlled by values 0 and 1 of microword selection bits $32{rAs} and $32{rBs} respectively. $p1 Both DMA address generation units share the bits $32{dmai[2:0]}, which control instruction lines $32([2:0]) of the AM2942 DMA address generation chips. Instruction line $32([3]) to those devices is set permanently to 0. A 0 on bit $32{dmasel} assigns this instruction to the module on $32(rB) bus, while forcing an "enable counters" operation in the module on bus $32(rA). Value 1 on $32{dmasel} has the opposite action, with $32{dmai[2:0]} controlling the module on $32(rA). Bits $32{dmaBcenL} and $32{dmaAcenL} are the complemented carry inputs to the counters in the units and can be used to individually enable the counts in the modules. For $32{dmamode} bit being 0 both address generators operate individually, with their completion signals: $32[dmaBdone] and $32[dmaAdone] indicating the completion of operation in each of the modules. 1 on $32{dmamode} joins the modules into one 32-bit address generator, with bus $32(rA[15:0]) being the more significant extension of $32(rB[15:0]), $32{dmaBcenL} being the count enable bit and $32[dmaBdone] signalling the completion of transfer. $p1 Right data bus $32(Data[15:0]) can be driven from local memory (memory read) for $32{rdatas[1:0]}=00, from $32(lD[15:0]) bus for 01, or it can invoke a read operation from APM for $32{rdatas[1:0]}=10. $b1 $a indent=5 $i0 $22(Important:) $t5 All APM transfers both in master and slave modes are 16-bits wide and are addressed from $32(lA[14:0]), $32(lB[15:0]). $a indent=0 $p1 Data can be written from right data bus into local memory (memory write) for $32{datad[1:0]}=00, into APM for 10, or it can be used to update (X,Y)=($32(lA[10:0]),$32(lB[10:0])) location in the framestore. $b2 $14(Sequencer) $p1 The data path is controlled by microprogram sequencer AM2910, which is a version of an older device AM2909 with added on-chip nanocoding of its control signals. The device is a 12-bit wide data path capable of addressing up to 4096 words of microcode, 512 of which can be ROM-based on the processor board. $p1 Microword field $32{seqi[3:0]} controls instruction bits $32{[3:0]} of the device. 0 on $32{srldL} forces an unconditional load of data from the data input into the sequencer's internal register. The contents of these 12 data input lines to the AM2910 is controlled by the $32(PL') output signal from the device, where a 0 selects $32{constant[11:0]} from the microword and a 1 selects $32{Data[11:0]} from the right segment. See the appropriate data sheet for the behaviour of the $32[PL'] signal for different instructions. $p1 The condition input to the sequencer comes from the AM2904. $p1 The initilise signal forces a "jump to 0" instruction in the sequencer. $n $14(Summary of microword format) $b1 $0 $l0 ==================+========================+================================+ mw[00]: const[0] | constant for the | constant for the lB bus of the | mw[01]: const[1] | AM2910 sequencer | data path | mw[02]: const[2] | | | mw[03]: const[3] | | | mw[04]: const[4] | | | mw[05]: const[5] | | | mw[06]: const[6] | | | mw[07]: const[7] | | | mw[08]: const[8] | | | mw[09]: const[9] | | | mw[10]: const[10] | | | mw[11]: const[11] | | | ------------------+------------------------+ | mw[12]: const[12] | | mw[13]: const[13] | | mw[14]: const[14] | | mw[15]: const[15] | | ==================+=========================================================+ mw[16]: lAs | lA bus source: 0 port A of 16 general registers | | 1 rA bus | | This is overriden by access from outside, forcing | | lAs[15:0] <= APM: 0,AD[31:17] | ------------------+---------------------------------------------------------+ mw[17]: lBs[0] | lB bus source: 00 port B of 16 general registers | mw[18]: lBs[1] | 01 rB bus | | 10 constant from the microword | | 11 | | This is overriden by access from outside, forcing | | lBs[15:0] <= APM: AD[16:1] | ------------------+---------------------------------------------------------+ mw[19]: rAs | rA bus source: 0 A bus DMA module | | 1 lA bus | | Access from outside forces rA[15:0] <= lA[15:0] | ------------------+---------------------------------------------------------+ mw[20]: rBs | rB bus source: 0 B bus DMA module | | 1 lB bus | | Access from outside forces rB[15:0] <= lB[15:0] | ------------------+---------------------------------------------------------+ mw[21]: ldatas[0] | lDATA bus source: 00 output from AM29203 alu shifter | mw[22]: ldatas[1] | 01 rDATA bus | | 10 lA[7:0],lA[15:8] (swopped bytes) | | 11 2904: zero,carry,negative,overflow | ------------------+---------------------------------------------------------+ mw[23]: rdatas[0] | rDATA bus source: 00 local memory[rB[15:0]] | mw[24]: rdatas[1] | 01 lDATA bus | | *10 APM data bus [lA[15:0],lB[15:0]] | | 11 | mw[25]: rdatad[0] | rDATA bus dest. : 00 local memory[rB[15:0]] | mw[26]: rdatad[1] | 01 | | *10 APM data bus [lA[15:0],lB[15:0]] | | 11 framestore [lA[15:0],lB[15:0]] | | Codings marked with "*" invoke appr. APM bus transfers, | | where the data path is the master of the bus. | | All above are overriden by access from outside, forcing | | READ : APM data bus <= local memory | | WRITE: APM data bus => local memory | ==================+==================================+======================+ mw[27]: spsi[0] | 29203 instruction code | mw[28]: spsi[1] | (see the appropriate data sheet) | mw[29]: spsi[2] | | mw[30]: spsi[3] | | mw[31]: spsi[4] | | mw[32]: spsi[5] | | mw[33]: spsi[6] | | mw[34]: spsi[7] | | mw[35]: shiftr\l | | ------------------+---------------------------------------------------------+ mw[36]: rfmaA[0] | A register address (read only) | mw[37]: rfmaA[1] | | mw[38]: rfmaA[2] | | mw[39]: rfmaA[3] | | ------------------+---------------------------------------------------------+ $n $l0 ------------------+---------------------------------------------------------+ mw[40]: rfmaB[0] | B register address | mw[41]: rfmaB[1] | rfmaB[4]: 0 general registers 1 framestore registers | mw[42]: rfmaB[2] | (write & read) (write only) | mw[43]: rfmaB[3] | 0000 colour | mw[44]: rfmaB[4] | 0001 plane write enable | | 0010 X display offset | | 0011 Y display offset | ==================+=========================================================+ mw[45]: AM04i[0] | AM2904 instruction bits [0:5] | mw[46]: AM04i[1] | (See the appropriate data sheet) | mw[47]: AM04i[2] | | mw[48]: AM04i[3] | | mw[49]: AM04i[4] | | mw[50]: AM04i[5] | | ------------------+---------------------------------------------------------+ mw[51]: condsel[6]| select input to AM2904(Iz,In,Ic,Iovr) | mw[52]: condsel[7]| 00 (zero,negative,carryout,overflow) | | 01 (dmaAdone,?,dmaBdone,?) | | 10 (?,?,?,?) | | 11 (.GND,?,?,?) | ------------------+---------------------------------------------------------+ mw[53]: shiftlk[0]| AM2904 shift linkage code | mw[54]: shiftlk[1]| (See the appropriate data sheet) | mw[55]: shiftlk[2]| | mw[56]: shiftlk[3]| | ------------------+---------------------------------------------------------+ mw[57]: AM04i[11] | AM2904 instruction bits [11:12] | mw[58]: AM04i[12] | (See the appropriate data sheet) | ------------------+---------------------------------------------------------+ mw[59]: AM04cem' | write enable' to program status register | mw[60]: AM04ceu' | write enable' to microprogram status register | ==================+==================================+======================+ mw[61]: dmai[0] | AM2942 instruction code (AM2942 i[3] = 0) | mw[62]: dmai[1] | (See the appropriate data sheet) | mw[63]: dmai[2] | | mw[64]: dmasel | 0 dmaB: dmai[2:0] dmaA: enable counters | | 1 enable counters dmai[2:0] | ------------------+---------------------------------------------------------+ mw[65]: dmaBcen' | complemented carry-in for the counters in dmaB | mw[66]: dmaAcen' | dmaA | ------------------+---------------------------------------------------------+ mw[67]: dmamode | 0 dmaB and dmaA operate as separate modules | | 1 dmaA is the more significant extension of dmaB | | dmaBcen' is the complemented carry-in | | and dmaBdone is the completion signal | ==================+=========================================================+ mw[68]: seqi[0] | instruction for AM2910 sequencer | mw[69]: seqi[1] | (See the appropriate data sheet) | mw[70]: seqi[2] | | mw[71]: seqi[3] | | ------------------+---------------------------------------------------------+ mw[72]: srld' | 0: sequencer register/counter := sDATA[11:0] | ==================+================================================+========+ mw[73]: waitreq | 1: wait request | | ------------------+------------------------------------------------+ timer | mw[74]: slow | | | ==================+================================================+========+ $b2 $12 $n