@part(soft.mss,root"rootfile.mss") @make(report) @newpage @chapter(Sequencer) @begin(quotation) This chapter describes a 16-bit wide data path, which is responsible for calculating the addresses of the successive microinstructions to be executed from microcode memory, thus implementing the flow of control of the microprogram . The sequencer supports fast interrupts, where the first interrupt serving microinstruction can follow immediately the microinstruction being executed when the interrupt request occurs. The resulting interrupt response time is less than 200ns. This, together with dedicated memory addressing capability in the controlled data path, can be used to implement a DMA-like mechanism in the microprogrammed hardware. @figure[ @blankspace(30 lines) @caption(interruptable sequencer - block diagram) @tag(interseqbd) ] @newpage The sequencer consists of 5 major functional blocks. @begin(itemize) @i[Microinstruction pointer register] stores the address of the currently executed microinstruction. 4k deep @i[local stack] of 16-bit words is used for storing the value of the microinstruction pointer register during interrupt processing, in microprocedure calls and can also be used for storing other information associated with these operations. @i[Next address generation block] calculates the address of the next microinstruction to be executed on the basis of information about the state of the controlled hardware. @i[Interrupt and initialise mechanism], upon initialisation forces the all O's microinstruction address. Upon interrupt, it pushes the newly calculated value for the microinstruction pointer register onto the stack and at the same time it injects the starting address of the interrupt-serving microcode. @end(itemize) @section(Internal data bus and stack) The stack contains 4k of 16-bit words and it si accessed from the internal bus sl<15:0> of the sequencer@foot(The second issue of the sequencer to be configured witha 32-bit data path will contain 32-bit wide stack and 32-bit wide sl bus, with 16 less significant bits (<15:0>) accessible to the sequencing hardware.) The source of data for this bus is specified by the microword field: @i[sls<1: 0>]. @figure[ sls< 1 0> 1 1 element on top of the stack 1 0 data< 15:0> from the controlled data path 0 1 microprogram register 0 0 newly generated microinstruction address @caption(Source of data for sl bus) @tag(souodf) ] Value 11 allows reading of the topmost element on the stack@foot(The stack does not have to be executing a pop instruction at the same time). Value 10 reads from the data bus of the associated data path (second board). This makes it possible to push external information onto the sequencer stack Selection of output from the next address generation block (for value 00) is a necessary condition to enable the interrupts. The operation of the stack is controlled by microword field: @i[stack<1:0>], as shown on fig @ref(stack micro). A "no operation" code is another necessary condition to enable the interrupts. Signal @i[stackfull] become 1 when there is only one free location left on top of the stack. It is available as condition< 13> to the sequencer. @figure[ stacki< 1 0> 1 1 no operation 1 0 reset 0 1 pop 0 0 push @caption(Stack microoperations) @tag(stack micro) ] A seperate stack enable signal @i[stacken] is used by the controller to enable (when 0) condition-dependent push/pop operations indicated by @i[stacki<1: 0>]. When no stack operations are required by the sequencer, @i[stacken] is set to 0 and the enabled stack can be used by the associated data path. The initialise signal to the sequencer does not reset the stack pointer, which should be initialised explicitly in microcode. @section(Next address function) The address of the next microinstruction to be executed is calculated as a result t of an ALU function, applied to its 3 input arguements A, B and carryin. @begin(itemize) The function is one of 8 implemented by an SN74381 ALU@foot(see the appropriate data sheet in the appendix.) and is selected by @i[salui<2: 0>] control signals. Arguement A can be all O's, for control signal @i[saluAen = 1.] For @i[saluAen = 0] it is the contents of the microprogram pointer register, when @i[saluAs = 0], or it is the contents of sl bus, when @i[saluAs = 1]. Similarly, argument B can be forced to all O's by @i[saluBen] = 1. Signal @i[saluBs] provides selection between a constant from the microword (when 0) and the contents of the external data bus (when 1). @end(itemize) In order to reduce the length of the microword signals @i[salui]<2: 0>, @i[carryin], @i[saluAen], @i[saluAs], @i[saluBen], and @i[stacken] are not directly controllable from the microword, but are defined as nanocoded functions of a sequencer instruction field: @i[sin]<4; 0>, and a selected status in information signal (condition)@foot(Otherwise, there would have to be two copies of each control field in the microword: one selected for condition = 0 and one for condition = 1.). The scheme provides 32 possible pairs@foot(with the value of condition used to select within each pair) of next address operations, defined through appropriate contents of nanocode ROM. There are 16 possible conditions to select from, using the condition select field: @i[conds el]<3: 0>. The upper 8 conditions (<15:8>) cover the status information available ble in the sequencer and the bottom 8 (<7:0>) provides status information from the associated data path. Microword bit @i[condinv] when 1 inverts @figure[ nr. condition 15 constant 0 (used to implement unconditional operations) 14 the state of the condition switch on the front panel 13 stackfull 12 bit <6> in byte 2 of the interface register 11 external condition signal on the pin of front edge connector 10 9 xblank : video horizontal blanking signal 8 yblank : video vertical blanking signal @caption(Status information (conditions) available in the sequencer) @tag(statiaits) ] the value of the selected condition, thus swapping the address selection operations in the pair selected by the field @i[sin]<4: 0>. The most useful ALU operations are add and subtract. As we are interested only in positive microcode addresses, we could limit these operations to addition only@foot(subtraction can be replaced by addition of complemented subtrahend plus one.). An example set of nanocoded operations is shown in fig @ref(nannexaddoper) together with the contents of nanocode ROM in the format: @i[salui]<2: 0>, @i[carryin], @i[salu Aen], @i[saluAs], @i[saluBen], @i[stacken]. Operations are described through resulting new values being loaded into microprogram pointer register (here abbreviated to MPR). @section(Interrupt and Initialise) The initialise signal forces the microinstruction address to all 0's. The control over the initialise signal is described in the chapter containing the operational instructions for the kit. Interrupt-serving microcode is invoked by forcing the address of the required starting microinstruction on the microcode address bus and pushing the newly calculated microinstruction address of the interrupted microcode onto the stack. These starting addresses as well as the priority for 4 possible external interrupt lines are stored in a seperate interrupt vector ROM. Interrupts can be disabled with immediate effect through not satisfying one of the previously mentioned necessary conditions (sls<1: 0> = 00 and stacki<1 0> = 11) or using a microcode-controlled interrupt disable flip-flop. The flip-flop is controlled by the microword bits: @i[intenJ], @i[intenK] which also take effect immediately. The value 10 enables interrupts (third necessary condition), 01 disables them and 00 leaves the state of the flip-flop unchanged from the previous microinstruction. @newpage @figure[ @blankspace(34 lines) @caption(Nanocoded next address operations) @tag(nannexaddoper) ] @section(Current setup: connections and interrupt vector ROM) Interrupt lines <3:2> are connected to bits <3:2> of the APM interface interrupt register (see the appropriate chapter). To increase the effectiveness of user-implemented debugging microcode, these signals are given the highest priority and are treated as a pointer to 3 vectors in interrupt ROM@foot(starting address for interrupt microcode) (hex): 0400, 0480, and 0500 for interrupt signals being: 01, 10 and 11. Line <1> has a priority over <0> and they point to values 0600 and 0700 in interrupt vector ROM respectively. @section(Examples of Operation) The following figures show the activation of data paths for some sample operatio ns of the sequencer. A summary of sequencer control signals, together with their assignment to the bits of the microword can be found in the appendix of this document. @newpage @figure[ @blankspace(20 lines) @caption(Example of sequencer operation: continue with external stack access and relative jump) @tag(exaofseqoper: con) ] @figure[ @blankspace(20 lines) @caption(Example of sequencer operation: microprocedure call and return) @tag(exampofseqoper: micro) ] @newpage @figure[ @blankspace(25 lines) @caption(Example of sequencer operation: interrupt accept and return) @tag(examofseqoper: inter) ] @newpage @chapter(Multichannel I/O controller) The data path of the controller consists of a central data bus and two (left and right address generation units. @figure[ @blankspace(30 lines) @caption(Multichannel I/O controller - block diagram) @tag(MultiIcont-blodia) ] @newpage @section(Data bus of the controller) Although most of the microcode-controlled devices on the central bus are 16 bits wide, the bus itself is 32 bits wide allowing for full, 32-bit word transfers between the local (buffer) memory and APM store. The width of transfer is controlled by bits @i[mmi<1: 0>] of the microword. Transfers are 32-bit, 16-bit and 8-bit wide for control bits being 10, 01 and 00 respectively. The bus is byte aligned, which allows it to interface to input/output devices of different width. Source and destination selection for the bus is achieved through fields @i[datas <3: 0>] and @i[datad<2: 0>] of the microword. Field @i[dev]<2: 0> contains the address of the input/output device, indicated by an all O's entry in a data bus source/destination field. @figure[ datas<3 2 1 0> 1 1 1 1 Product from AM29517: less significant half 1 1 1 0 Product from AM29517: more significant half 1 1 0 1 AM29116 Y bus 1 1 0 0 ID bus: data bus of left address generator 1 0 1 1 rD bus: data bus of right address generator 1 0 1 0 Sl bus: sequencer stack bus 1 0 0 1 constant<15:0> from microword 1 0 0 0 0 1 1 1 local memory (memory read) 0 1 1 0 framestore 0 1 0 1 APM interface (read from APM) 0 1 0 0 0 0 0 0 device(dev<2:0>) @caption(Data bus source selection) @tag(databusoursele) ] @figure[ datad<2 1 0> 1 1 1 local memory (memory write) 1 1 0 framestore 1 0 1 APM interface (write to APM) 1 0 0 multiplier control register 0 1 1 register address register 0 0 0 device(dev<2:0>) @caption(Data bus destination selection) @tag(databudesselec) ] @subsection(AM29116 data path) A simplified block diagram of the AM29116 data path is shown on fig @ref(AsimpblodiaofAM29). The data bus Y<15:0> of the device can be read into the data< 15:0> under the address 1101. A 16-bit instruction is provided in the field @+[pri]<15: 0> of the microword. For microcode bit @i[prarsel] = 1, instruction bits <4:0>, used for addressing within the 32-register block of AM29116 are over-ridden by the contents of a writeable register address register. Microcode bit @i[prnsel], when 1 causes instruction bits <9:12>, responsible for parametrising shift operations, to be over-ridden by the contents of the left address generator data bus: ID<3:0>. A 0 on @i[prdle'] makes the data input latch to AM29116 transparent, and a 1 disables it. A 0 on bit @i[prsre'] enables the update of the data path status register. A 0 on @i[prien'] is a necessary condition to enable writes into any of the registers. A detailed functional description of the device, together with the instruction codes, codes is provided in the appendix. @figure[ @blankspace(25 lines) @caption(A simplifed block diagram of AM29116) @tag(AsimpblodiaofAm29) ] An AM29517 high speed parallel 16 x 16-bit multiplier takes X and Y arguments from data busses of address generation units, and returns both halves of the 32-bit result onto the central data bus. X argument register can be loaded from bus lD<15:0> by setting microword bit @i[mlenx'] to 0. Similarly, a 0 on bit @i[mleny'] loads rD< 15:0> into Y argument register. More significant and less significant halves of the product register can be read onto the central data bus for @i[datas<3: 0>] set to 1110 and 1111 respectively. A 40ns multiply time guarentees the availability of the result directly in the microinstruction and seperated inputs and output allow for the pipelining of operations. Multiplier control bits: X@-[M], y@-[M], RND, FA, and ENP' are provided from writeable register, which for @i[datad<2: 0>] = 100 is loaded from data<5:0>. A detailed functional description of the device, together with the possible formats ats of number representation is provided in the appendix. @section(Address Generators) There are two, left and right, address generation units, and each contains a set of 16 16-bit dual-ported registers, where the concatentation of the outputs A and B within each of the sets forms a 32-bit address bus. Microword control fields are similiar for both units and in the following description variable @+[*] c {l,r} is used when describing these similiar fields. @+[*] = 1 makes the description applicable to the left unit and @+[*] = r applies it to the right unit. For microcode bits @+[*]@i[As] and @+[*]@i[Bs] being 0, ports A and B of the unit register set drive more and less significant halves: @+[*]A<15:0> and @+[*]B<15:0> of the address busses respectively. All registers in both units are addressed through 3 shared more significant address bits and individual least significant bits: @+[*]@i[raA0,] @+[*]@i[raB0] for each one of the ports. The 3 more significant bits can come from a shared microword field @i[ra<3: 1>, or from the writeable register address register, mentioned in the previous section. on. Bit @+[*]ras, through values 0 and 1, implements the selection between ra<3: 1> and the address register, individually for each of the right and left sets. A 1 on @+[*]@i[As] or @+[*]@i[Bs] drives the appropriate @+[*]A<15:0> bus with its left/right counterpart (e.g lA<15:0> obtains data from rA<15:0> obtains data from lB<15:0> etc.). Address for pirt B is also the address of the destination register to be loaded with the value appearing on @+[*]D<15:0>, when microcode bit rw' = 0. Bit @+[*]Ds through values 1 and 0 provides the selection of data for @+[*]D<15:0>] between the central data bus Data<15:0> and the local modidier circuit. The modifier adds/subtracts the modify value to/from contents of @+[*]D<15:0> , for micrpcode bit @+[*]@i[incr] being 1/0. For @i[modify]<2: 0> = 111 the modify value comes from @+[*]A<15:0>, while the other values of that field are used to address a shared modify ROM. The contents of the modify ROM are shown on fig @ref(Addrmodval). @figure[ modify< 2 1 0> 1 1 1 modify value comes from @+[*]A<15:0> 1 1 0 32 1 0 1 16 1 0 0 8 0 1 1 4 0 1 0 2 0 0 1 1 0 0 0 0 @caption(Address modify values) @tag(Addrmodval) ] The result of modification can be stored back into the register for port B, it can be used as an argument for the multiplier, or it can be read into the central d l data bus. Overflow while modifying the less significant half of the address should be followed by the appropriate modification of the more significant half. Left address bus is connected to the interface to the APM and the right one forms the address bus of the local memory. In effect each unit provides 8 32-bit register-counters which can give independe nt DMA-type support for 8 individual channels, with individually selected unit of c count (width of transfer) for each of them. A pair of such channels, one from left and one from right units, provides a fast@+[13] block move capability between local (buffer) memory and main APM store. Varied-length count capability on registers of the AM29116 provides the necessary, concurrent length -of-transfer count. A and B parts of the left address bus are pin-compatible with the X and Y coordinate address busses of the framestore. For graphics requiring two seperat e counters, B port of left unit can be used to drive the Y coordinate and A port of right until unit can be used to drive the X coordinate. @section(Status Information available from the controller) Status information (conditions) available from the controller, together with their codings on @i[condsel<]3: 0> are shown of fig @ref(stainfavaitcon). The generation of condition CT in AM29116 can be controlled by the field @i[pri<4 :0>] of the instruction, or by lD<3:0>, for @i[condsel>3: 0>] being 0000 and 0111 respectively. @figure[ no condition 7 condition output CT(lD<3:0>) from AM29116 6 carry from right address modify module 5 carry from left address modify module 4 overflow from AM29116 ALU 3 zero from AM29116 ALU 2 carry from AM29116 ALU 1 negative from AM29116 ALU 0 condition output CT(@i[pri<4: 1]) from AM29116 @caption(Status information (conditions) available in the controller) @tag(stainfavaitcon) ] @chapter(Advanced Personal Machine graphics processor-interpreter) The basic grapics configuration consists of a framestore and a microprogrammed @foot(A seperate microcode RAM can be provided for dynamic loading of microcode, for microcode development work.) data path, which calculates new pictures from their structured descriptions residing in the APM store. It is assumed that these descriptions will be manipulated by multiple processes in the APM system like: window managers text and graphics editors, user-defined sub-window managers (e.g. text, buffer and menu subwindows within the editor), animation programs etc. The speed of the data path producing new contents of the framestore should give a new frame every 2-3 vertical scan times, which together with double-buffering scheme will give 12-25 new frames/sec. The processor/interpreter has its own, expandable local memory for stacks and storing of most commonly used graphics functions. The bottom 8k bytes usually hold microcode jump vectors and up to 2 types of character font, which are some of the possible leaf functions in the picture description structure (acyclic g raph). The processor fits onto a single board, together with 16k bytes of local store (8k of ROM and 8k of RAM) and 512 words of ROM-based microcode. The framestore contains 1024x1024 pixels (4, 8, 12 or 16 bits per pixel) of display memory and a simple controller to drive the monitor and implement write operations into the memory. @subsection(Data Path) The block diagram of the interpreter data path is shown on fig @ref(grapro-int-blodia). The data path consists of 2 major sections, each of them built upon 3 16-bit busses: two for address and one for data. The left section has a general data processing capability and its address busses and framestore's X and Y coordinate addresses (individually). The right section is geared towards block moves of data and is capable of driving its address lines: rA<15:0> and rB<15:0> with consecutive values as one 32-bit address, or as two seperate 16-bit counters. Right data and address lines supp ort local memory (with the bottom 4k words of ROM and 4k of dual-ported RAM available locally on the processor board). The right data bus is also used to support most of the data transfers within the system. Data can be transferred between the left and right counterparts of the sections. @figure[ @blankspace(30 lines) @caption(Graphics processor-interpreter - block diagram) @tag(grapro-int-blodia) ] @subsection(Left section) The major component of the left section is a 16-bit general-purpose data path, built out of 4 AM29203 4-bit "superslices", supported by a carry-lookahead and an AM2904 status and shift control units. Detailed functional descriptions of these units are provided on the data sheets in the appendix to this document. The AM29203 contains 16 16-bit dual-ported registers, where ports A and B can be output onto busses lA<15:0> and lB<15:0> for the values of microword fields lAs = 0 and lBs<1:0> = 00 respectively. Value 1 on lAs drives lA<15:0> and rA<15:0 > and value 01 on lBs<1:0> drives lB<15:0> with rB<15:0> (address busses of the right section). Value 10 on lBs<1:0> injects a 16-bit constant<15:0> microword field onto lB<15:0>. The data bus lD<15:0> can be driven by the output from AM29203 alu shifter, for the field ldatas<1:0> = 00. For ldatas<1:0>=01 it obtaines the data from the right data bus: Data<15:0> and for 10, it provides swopped bytes of the bus lA<15:0>: lA<15:8>. The value 11 reads (zero,carry,negative,overflow) status bits from AM2904 onto lD<3:0>. Microcode bits shiftrV and spsi<7:0> provide instruction bits <8:0> for the AM2903 and rfmaA<3: 0>, rfmaB<4:0> provide the addressing for the A and B register output ports. Bit shiftrV is also used as instruction bit <10>, controlling the direction of shift in the shift linkage part of AM2904. Register address for port B is also an address for register write operations from bus lD<15:0>, 16 bottom registers, addressed by OrfmaB<3:0> are the interna l registers of the AM29203 and the top 16 addresses cover control registers of external devices connected to the data path. When connected to the basic frame store, register addresses 10000, 10001, 10010 and 10011 provide write a access to colour, plane write enable, X display offset and Y display offset registers. Register addresses 10110 and 10111 are used to load two register address registe rs, for ports B and A respectively. The contents of these registers are used t o replace 4 least significant bits in register address, whenever the correspondi ng 4 least sifnificant bits in the microword are all 1's. Microword fields AM04i<12:11>, shiftlk<3:0> and AM04i<5:0> control instruction bits <12:0> of AM2904. The device provides the carryin signal to the AM20203, all the necessary linkage for shifts, supports the necessary status information and also generates the condition signal for the sequencer. The functional description of the device is provided in the appendix. Bits AM04cem' and AM04ceu', when 0, enable the writes into the device's program and microprogram status registers. The AM2904 can generate on its condition output a variety of functions applied to the values of its 4 input lines and internal status bits. All the status information in the data path is fed into these inputs, and the multiplexing of the conditions onto 4 inputs lines is controlled by the microword bits: condsel<7:6>. For those bits being 00, inputs (lz,ln,lc,lovr) are connected to the (zero, negative, carryout, overflow) outputs from AM29203. 01 provides a vector (dmaAdone, ?, dmaBdone, ?) of the completion signals from the right segment DMA modules and a vector (GND, ?, ?, ?), under 11 provides a constant for unconditional operations of the sequencer. @subsection(Right section) Address busses rA<15:0> and rB<15:0> of the right section can be driven from their designated DMA address generation units, or from their left counterparts. The selection is controlled by values 0 and 1 of microword selection bits rAs and rBs respectively. DMA generation units share the instruction bits dmai<2:0>, which control instruction lines <2:0> of the AM2942 DMA address generation chips. Instructio n line <3> to those devices is set permanently to 0. A 0 on bit dmasel assignes this instruction to the module on rB bus, while forcing an "enable counters" operation in the module on bus rA. Value 1 on dmasel has the opposite action, with dmai<2:0> controlling the module on rA. Bits dmaBcen' and dmaAcen' are the complemented carry inputs to the counters and they can be used to individually enable the counts in the modules. For dmamode bit being 0 both address generators operate individually, with the completion signals dmaBdone and dmaAdone indicating the completion of operation in each of the modules. 1 on dmamode joins the modules into one 32-bit address generator, with bus rA<15:0> being the more significant extension of rB<15:0>, dmaBcen' being the count enable bit and dmaBdone signalling the completion of transfer. Right data bus Data<15:0> can be driven from local memory (memory read) for rdatas<1:0> = 00, from lD<15:0> bus for 01, or it can invoke a read operation from APM for rdatas<1:0> = 10@foot(All APM transfers in master mode are 16-bits wide and are addressed from lA<14:0>, lB<15:0>.). Data can be written from right data bus into local memory (memory write) for datad<1:0> = 00, into APM for 10, or it can be used to update (lA<10:0>,lB<10:0> ) location into the framestore. @section(Sequencer) The data path is controlled by microprogram sequencer AM2910, which is a version of an older device AM2909 with added on-chip nanocoding of its control signals. The device is a 12-bit wide data path capable of addressing of up to 4096 words of microcode, 512 of which are ROM-based on the board. Field seqi<3:0> controls instruction bits <3:0> of the device and a 0 on srid' forces an unconditional load of data from the data input into the sequencer's internal register. The contents of the 12 data input lines to the AM2910 is controlled by the PL' output signal from the device, where a 0 selects constant<11:0> from the microword and a 1 selects Data<11:0> from the right segment. The condition input to the sequencers comes from the AM2904. The initilise signal (from front panel, from the APM bus or from reset register) forces a "jump to 0" instruction in the sequencer. The microword format for the data path, together with short summary of the funct ion of seperate fields, is provided in the appendix. @newpage @section(Framestore) @begin(itemize) several display memory circuits, each corresponding to a 1024x1024 array of bits for the display, together with their associated 16-bit video shift registers. one memory controller circuit, responsible for all read/write operations in the display memory as well as for displaying its contents on the screen. @end(itemize) @subsection(Display memory) The circuit contains the video memory (64k DRAMs), 16-bit video shift register and a simple data path used to implement a variety of read/write operations. These operations support also the capability to take fast snapshots with TV camera, where the apppropriate bit of the digitised video input signal is shifted through the video regester, straight into the output monitor, while consecutive 16-bit words can be captured into the memoty. There are 4 memory circuits on one board, and they can be configured as: @begin(verbatim) 1. 4 planes with 1024x1024 pixels (colour monitors) 2. 2 planes with 2048x1024 pixels (high resolution monochrome) 3. 1 plane with 4096x1024 pixels (4 boards will store a picture that can be output to a 4096x4096 pixsels laser printer) @end(verbatim) The frame can be run with the video frequency of up to 50MHz. In order to obtain much higher frequencies, like 200 MHz required by some recently appearing very high resolution monitors, static memories would have to be used, reducing the number of circuits to one per board. Only minor modifications of the circuit design are required to support a 2048x2048 bit array, once 256k memories become available. In the basic version the supporting data path in the memory circuit has been reduced to a minimum, allowing only for a simple "write pattern" instruction. @subsection(Display memory controller) Display memory controller can control frames with up to 16 planes@foot(Planes should not be confused with memory circuits as each plane can contain 1, 2 or 4 such circuits.) (16 bits/pixel). Through programmable timing circuit it can support a variety of colour and monochrome monitors. The controller interface to the rest of the system can span from a simple direct APM bus interface, which maps the framestore into the APM address space, up to a high-performance autonomous graphics processor-interpreter in APM. The interface consists of: @begin(itemize) two 12-bit coordinates addresses: X<11:0> and Y<11:0> 16-bit data bus: D<15:0> control lines: RD\WR, l<2:0> defining the operations of the framestore with reference to the coordinate addresses and data. timing lines to implement synchronisation with the device driving the framestore @end(itemize) The memory controller has several writeable frame control registers: @begin(itemize) colour registers for holding the colour to be used in some write operations into the frame plane address register for some of the read and write operations plane write enable register, being the map od planes with enable write operation s X offset register specifying vertical position of the monitor display window within the frame Y offset register specifying horizontal position of the display window within the frame plane mapping register, specifying the way the planes are selected as addresses of the colour map memory @end(itemize) Offset registers indicate the starting position in the frame for the display circuit. They are useful when the frame size exceeds the resolution of the monitor and, with a frame over 2 times larger than the screen, they permit the use of double buffering during image calculation@foot(New picture is being calculated outside the screen and then, during the nearest vertical flyback, the screen is moved onto the updated area.) The circuit has several internal control signals and all operations are implemented by nanocoding these signals as functions of RD\WR and l<2:0>. An example collection of such operations is shown below@foot(Other operations can be implemented by providing different contents of the nanomemory.) @begin(verbatim) RD\WR,l<2:0> description 0000 read the contents of the pixel at (X,Y) into D<15:0> 0001 starting from (X,Y) to the right, read from plane [plane address register] into D<15:0> 0011 starting from (X,Y) to the right, read 16 consecutive bits from the planes into their plane read registers (there is one such register in each plane) 0100 using the addresses provided by the display circuitry, shift the whole frame through the colour map memory, and store the newly obtained pixels only in the locations indicated by 1's in the plane[plane address register] 0111 camera synchronization; transfer camera signal directly to the monitor 1000 write D<15:0> into a pixel at (X,Y) 1001 starting from (X,Y) to the right, write D<15:0> into the plane[plane address register] 1010 starting from (X,Y) to the right, put the contents of the colour register into pixels indicated by DA<15:0> 1011 starting from (X,Y) to the right, put the contents of plane read registers, back into their associated planes with the patteren of write indicated by D<15:0> 1111 camera write; capture full scan of the screen into the frame @end(verbatim) During read and write operations on the frame, the memory controller handles appropriate WAIT and READY timimg lines, to synchronize the external processor with the framestore. Writing into control registers does not require such synchronization. The basic version contains only colour, plane write enable and offset registers. It It can only execute the "write D<15:0> pattern of colour" instruction (1010 in the example). The controller is located on a single board, together with 4 memory circuits, providing an autonomous 4-planes framestore. Current version gives every second display memory cycle to the external accesses, allowing for the speed of update to be comparable with that of the displaying, provided the driving processor can utilize this offered bandwidth. @subsection(Driving the framestore) There is a whole range of possibilities for providing a stream of coordinates, data and instructions, that would result in the desired picture being created on the display. These can vary from a simple interface to a sophisticated processor. Simple interface maps the framestore addresses into the APM address space, with the graphics algorithms being run in some processor on the system bus. Although significantly slower than the other possibilities it is the cheapest way of driving the frame, and also allows for initial, graphics experiments to be conducted in a user-chosen high-level language. @chapter(Local Memory) The local memory unit contains 64k bytes of fast, static, random access memory per board. Memory is dual-ported, providing independent accesses from local processor and from APM bus. Accesses from local bus are byte-aligned and can be word, half-word or byte wide, with the width of access controlled by the lines width<1:0>. These lines are driven directly from the mmi<1:-> field in the processor microword. When accessed as a slave from the APM@foot(The board has seperate bus address switches for its local and APM base addresses.), the board raises a wait request to the local processor timer. This request can be accepted in every microinstruction cycle, giving response time of less than 200ns. The timer is stopped, halting the local processor, and a wait acknowledge signal enables the transfer between the APM and local memory via its APM port@foot( For the details of APM bus protocol see the appropriate document.). The memory can be used for storing jump vectors for the microcode and leaf functions for the graphics processor. It can serve as a feneral-purpose workspace, or as a buffering space for the input/output controller. @chapter(Input/Output devices) A variety of input/output devices can be supported by a data path controlled by an interruptable sequencer. They can vary in speed as well in the width of interface. Most of the bit-serial devices, like the Ethernet transmitter/receiver presented here as an example, consist of shift registers to serialize/deseriali ze outgoing/incoming data with associated control, plus first-in-first-out memory, providing some asynchrony between the clock of the external bit-stream on one end, and the operation of the buffering hardware on the other. Bit-str eam control logic is different for different devices, but their FIFI interfaces (usually byte wide) are very much alike. Another example of such a device could be the interface presented by some of today's integrated disk read/write head(s) through read/write interface FIFOs. It should, of course , be appreciated that the possibility of using this type of general data-path for handling such devices does not mean that there is not a significant amount of design effort required to tailor the microcode and parts of the hardware to each individual case. Nor is it claimed that this approach would necessarily provide the most cost-effective solution for a large scale stable production run. An attempt will be made to provide analog-to-digital and digital-to-analog converters as input/output devices for the second part of the exercise. @section(Video monitor and timer) The block diagram on fig. shows the organisation of a simple laser-printer controller, which under control from the APM data bus can be used to send an array of bits from APM main memory, bit-serially to the printer. The device consists of a 64-words deep FIFO, 32-bits wide, with a 32-bit shift register on the output end. The control consists of 3 AM2940 DMA address generation units, responsible for the timing of the output and addressing of the APM memory, plus some printer control, and APM interface logic. These consist mainly of circuits implementing appropriate handshakes on both printer and APM interfaces and of a number of control and status registers accessible from the APM. By bypassing the APM interface and providing the address generation units with different nanocode, which takes away the synchronising initiative from the external world (as is necessary for the printer) and replaces it with synchronisation for the video monitor, the device could be used to drive a video monitor directly from the microprogrammed data path. An interrupt generated by the horizontal blanking signal would result in the processor sending the appropriate video line to the FIFO, seen as a 32-bit output register on the bus. The vertical blanking signal can be used for the necessary frame synchronisation. A number of schemes for producing video lines is possible and they may be explored in the second part of the exercise. @figure[ @blankspace(30 lines) @caption(Block diagram of a laser printer/video monitor controller) @tag(blodiaofalasprint/vidmoncont) ] @chapter(Operating the kit) This chapter contains a set of guidelines as to how to load and run the microcode, together with a brief description of how to control its execution. @section(Front Panel) There is a simple stand-alone front panel that can be connected through 16-way ribbon cable to the connector on the sequencer or graphics processor/interpreter board. The panel contains 4 spring-loaded switches which provide manual control over the execution of microcode. All the keys are debounced on the panel board. Two of them have momentary action and two others are used to toggle on-board flip-flops, with 1 in a flip-flop indicated on an associated red LED. They are used to support control signals which should persist for indefinite periods of time. @begin(verbatim) INIT This momentary action key provides a signal which resets everything, forces on all 0's starting address of the microcode, and puts the timer in the wait state. HRQ The output of the flip-flop controlled by this key provides one of possible wait request signals to the timer. When the signal is set to 1 the timer is put into the wait state for every micro- instruction cycle. A wait acknowledge signal from the timer is monitored by a green LED associated with the HRQ key. EXE This momentary action key forces the exit from the wait state of the timer. Together with the HRQ switch (set to 1) it can be used to single-step through the microcode. COND The output of the flip-flop controlled by this key is available as condition <14> to the sequencer. It can be used for manually controlled execution of segments of microcode. A typical example would be the testing of the state of the condition by the microcode interpreting a set of machine instructions, once every interpretation loop. A resulting wait state invoked by the microcode, together with the action of EXE key, allows single-stepping through the interpreted machine instructions. @end(verbatim) Front panel-type actions can be also achieved from the APM bus through 3 control registers, available in the sequencer. One 16-bit and two byte-wide registers form a 32-bit word, accessible from the bus. During the exercise, this register will be located at FFEFFFFC in the APM address space. @begin(itemize) The lower 2 bytes ( 0 and 1) form a 16-bit register, writeable from the APM and readable as device register 0 from the data path. Another 16-bit register that can be read on those bytes from APM bus, is accessible as output device register 0 for the data path. A write into byte 2 puts a 4-bit interrupt vector into bits <3:0>, where during the exercise, only bits <3:2> are connected to the sequencer interrupt lines <3:2>. One of 3 possible interrupt vectors can be invoked when at least one of those bits becomes 1. Bits <7:5> of byte 2 correspond to switches HRQ, COND and INT on the front panel. Bit <7> = 1 forces a wait state in every microinstruction cycle, bit <6> is available as condition <12> to the sequencer, and a 1 written into bit <5> resets the whole data path. A write of any value into byte <3> is equivalent to pressing the EXE key on the front panel. @end(itemize) @section(Loading the microcode) On initialisation (from RSTL on APM bus, INT on front panel or from interface register) the microcode address is forced to 0 and the timer is forced into the wait state. This setup allows loading of the complete microcode, without the need for any initial part being resident on local ROM. The execution of microcode can be started by pressing the EXE switch, or through a write into byte 3 of the interface register. @subsection(Microcode RAM) The microcode RAM is organised into 128-bit words and can take up to 1Mbyte of APM address space. This memory is organised as write-only from APM bus and read-only from the microcode bus. Only 96 out of the 128 microcode bits are actually implemented on the current memory boards. For the purpose of the exercise the microcode RAM address space will start at location FFF00000 on the APM bus. Thus, a microword seen at microcode address MMMM from the sequencer will be located at FFFMMMM0 for the APM. Each microword takes 16 consecutive bytes of APM address space, with the byte containing least significant bits located at the topmost byte location. Thus bit 0 of a microword at microcode address MMMM corresponds to bit 0 of byte FFFMMMMF on the APM bus. There is (will be) a loader program: "mload", which takes an assembled microprogram in the formatshown below, puts it into the microcode memory and then starts its execution. A text file to be loaded using "mload" starts with declaring the format of the microwords to be loaded, followed by the actual microcode. The format declaration as well as consecutive microinstruction are terminated by newlines and the whole sequence is terminated by end-of-file. A format declaration is a sequence of decimal numbers, seperated by spaces, specifying the widths of consecutive fields in the microword, starting with the field containing bit 0. Each microinstruction takes the form of a sequence of hexadecimal values for the consecutive microword fields. Field entries are seperated by spaces and are presented in the same order as the format declaration. Location directives may be interspersed among the microinstructions. These take the form at an at-sign (@) followed by an optionally signed hexadecimal value. An unsigned value represents an absolute location within microcode RAM and a signed value indicates a location relative to the current position (that is, the address of the last loaded word plus one). These values are microcode RAM addresses, that is 128-bit word (not byte) addresses. @begin(verbatim) :== NL :== l :== lNL :== {} :== @{+l-} :== l :== l :== 0l1l2l3l4l5l6l7l8l9 :== 0l1l2l3l4l5l6l7l8l9lAlBlClDlElF @end(verbatim) @section(Bebugging) @subsection(single-stepping) Single stepping can be done manually from the front panel or under program control from APM bus. In wait state the timer still supports all the APM bus handshake signals, allowing access to the control registers of the data path and its dual-ported local memory. It is possible to make provisions for the aquisition of additional information from the kit by incorporating interrupt microcode invoked by interrupt bits <3:2> from the APM interface. This can provide access to data path registers which normally are not accessible from outside. @end(quotation)