A Description of the ICL 2970 System
Philip A.F. Hartley
Computer Science 4 Project
Version 2.2
Contents
0. Introduction.
1. Hardware Description.
1.1 The Order Code Processor
1.2 The Store Access Controller.
1.3 The Store Multiple Access Controller.
1.4 The Store Input Controller.
1.5 Peripherals and Controllers.
1.6 The RCO 2970 Configuration.
2. Virtual Addressing and Protection.
2.1 Virtual Address Format.
2.2 Protection.
2.3 Segment Tables.
2.4 Page Tables.
3. The Image Store.
3.1 Registers internal to the OCP.
3.1.1 Visible Registers.
3.1.2 Invisible Registers.
3.2 External registers.
4. New Range Order Code.
4.1 The Stack.
4.1.1 Stack Front (SF).
4.1.2 Local Name Base (LNB).
4.1.3 Stack Segment Number (SSN).
4.2 Other User Addressable Registers.
4.2.1 Extra Name Base (XNB).
4.2.2 Accumulator (ACC).
4.2.3 B Register.
4.2.4 The Descriptor Register (DR).
4.2.5 Overflow (OV).
4.2.6 The Condition Code (CC).
4.2.7 Program Mask (PM).
4.2.8 The Real Time Clock (RTC).
4.3 Descriptors.
4.3.1 Vector Descriptors (type 0).
4.3.2 String Descriptors (type 1).
4.3.3 Descriptor Descriptors (type 2).
4.3.4 Miscellaneous Descriptors (type 3).
4.3.4.1 Code Descriptors (subtype 32 or 34).
4.3.4.2 System Call Descriptors (subtype 35).
4.3.4.3 Escape descriptors (subtype 37).
4.4 Addressing Modes.
4.4.1 Primary Addressing Modes.
4.4.2 Secondary Addressing Modes.
4.4.3 Tertiary Addressing Modes.
4.5 Instructions.
4.5.1 Stack Control Instructions.
4.5.2 DR Instructions.
4.5.3 B Instructions.
4.5.4 Control Transfer Instructions.
4.5.5 ACC Instructions.
4.5.6 Computational Instructions.
4.5.6.1 Logical Operations.
4.5.6.2 Decimal Operations.
4.5.6.3 Fixed Point Functions.
4.5.6.4 Floating Point Functions.
4.5.7 String Instructions.
4.5.8 Sundries.
5. Interrupt Structure.
0. Introduction.
This document is not intended to be a fully comprehensive guide
to the 2970 but rather a general outline of the basic concepts
involved in the system. The information is a combination of that
obtained from the references and that gleaned from people who are
currently working on the system.
The ICL 2900 machines are a series of general purpose
computers, spanning a range of processing powers. The 2970 is the
medium performance machine in the series and ICL are hoping for an
equivalence in computing power to that of the 1906A, although this
has still to be shown in practice.
1. Hardware Description.
The main system components are:
1. OCP - order code processor
2. SAC - store access controller
3. SMAC - store multiple access controller ( + store)
1.1 The Order Code Processor
The 2970 OCP is the system component which interprets the
order code. It is microprogrammed and facilities do exist to
allow users their own microcode routines in order to enhance
the performance of certain applications. Instructions are
overlapped in the following stages:
1. Instruction fetch and decode.
2. Operand address computation and fetching.
3. Operand buffering.
4. Arithmetic computation.
Each OCP has 3 outlets (port interfaces, see SMAC),
fanned out from a single interface, for connection to store
units (via SMAC). The 2970 can have 1 or 2 OCPs.
OCP - OCP and OCP - SAC communication is done via the
Direct Wired Interface which carries activates and
interrupts.
1.2 The Store Access Controller.
The SAC multiplexes the transfers of up to 8 peripheral
controllers to and from store. The link between the SAC and
the peripheral controller - the Trunk Interface - is 2 bytes
wide and can handle data at up to 4 Mb/s. The SAC, like the
OCP, has 3 port interfaces fanned out from a single interface.
The SAC can have either 4 or 8 trunk links. A 2970 system
can have at most 2 SACs.
1.3 The Store Multiple Access Controller.
The SMAC controls multiple SAC and OCP accesses to the
store. The SMAC has 4 ports of which 2 are dedicated to
OCPs and 2 are dedicated to SACs. SAC ports have
priority on simultaneous access and priority within pairs is
cyclic.
The port interface has an 8 byte data path with a bandwidth
of 16 Mb/s, 26 address lines (which carry a real byte address)
and various control lines. Store connected to the SMAC can be
between 1/4 and 2 Mb in increments of 1/8 Mb. A 2970 can
have up to 3 SMACs (i.e. a maximum of 6 Mb of store).
The SMAC functions are:
READ read 2 words from store
WRITE write 2 words to store
PARTIAL write write less than 2 words to store
1.4 The Store Input Controller.
Another useful, but not necessary, system component which
will be available on early models is the Store Input
Controller (SIC). This is used to input engineers' test
programs straight into store, normally from a paper tape
reader.
1.5 Peripherals and Controllers.
Peripherals are connected to peripheral controllers by the
New Range Device Interface. This interface is 1 byte wide
and allows 1900 and System 4 peripherals to be connected as
well as New Range peripherals. The types of controllers
available are:
GPC - general peripheral controller. Used for slow devices,
OPER (operating station), mag. tape, the 7905, etc.
SFC - sectored file controller. Used for handling fixed head
disks.
FPC - (DFC) file peripheral controller (disk file controller)
Used for handling the Exchangeable Disk Systems.
CNP - communications network processor. Handles remote
communication.
Note that all peripheral controllers work on virtual
addresses. I/O is normally done through Public Segments (see
below) so any change in the Public Segment Tables will
necessitate the re-initialisation of the peripheral
controllers.
1.6 The RCO 2970 Configuration.
The present RCO 2970 configuration is:
p +-------+ p
+-------+ o | | o +-------+
| |-------r-------------| S I C |-------------r-------| |
| S | t | | t | S |
| M |------- -------\ +-------+ /------- -------| M |
| A | i | | i | A |
| C |-------n-----\ | +-------+ | /-----n-------| C |
| | t | | | | | | t | |
+-------+ e | \-----| O C P |-----/ | e +-------+
| | r | | | | r | |
| store | f | +-------+ | f | store |
| | a | | | a | |
+-------+ c | | | c +-------+
1/2 Mb e | direct wired | e 5/8 Mb
| interface |
| | |
| | |
+-------------------------+
| |
| S A C |
| |
+-------------------------+
| | | | |
| | | | |
trunk interface
| | | | |
/-----------------/ | | | \----------------\
| | | | |
| /--------/ | \--------\ |
| | | | |
| | | | |
+------+ +------+ +-------+ +-----+ +-----+
| | | | | | | | | |
| GPC1 | | GPC1 | | CNP | | FPC | | SFC |
| | | | | | | | | |
+------+ +------+ +-------+ +-----+ +-----+
| | | |
| | | |
n e w r a n g e d e v i c e i n t e r f a c e
| | | |
MT1 MT2 | |
| | 4*EDS 100 |
MT3 MT4 (4*100Mb) 2*FHD
| | (2*6Mb)
OPER S OPER S
| |
OPER M OPER M
| |
CR CR
| |
LP LP
OPER S and M, cr and LP are connected to both GPCs for
reliability.
2. Virtual Addressing and Protection.
2.1 Virtual Address Format.
A virtual address is a 32 bit quantity which is interpreted
as follows:
+--------------------+-----------------------+--------+
| | | |
| Segment | Word | Byte |
| | | |
+--------------------+-----------------------+--------+
0 13 14 29 30 31
Therefore a virtual memory can have at most 16K segments
containing up to 256K bytes each. The virtual address is
converted by hardware into a 28 bit real byte address by
accessing the Local Segment Table (via the Local Segment
Table Base register - LSTB) for references to segments 0 -
8K, and the Public Segment Table (via the PSTB) for
segments 8 - 16K. The LSTB and PSTB contain a segment
number limit. Therefore, there need not be segment table
entries for all 16K segments.
Public segments are common to all processes although local
segments can be shared between processes as Global Segments
(see below). I/O is normally done to and from public segments.
2.2 Protection Levels.
The method of enforcing protection levels on the 2900
system is by the Access Control Register (ACR). Each
process has associated with it an ACR whose value cannot be
altered unless the process is at the highest level of
privilege. A resource requiring protection has attached to it
a tag - unalterable unless at the highest level of privilege -
against which an accessing user's ACR is checked. If the ACR
is less than or equal to the value of this tag (i.e. the lower
the value, the more privileged is the process) then access is
allowed, otherwise an interrupt occurs.
2.3 Segment Tables.
1 2 3 11 14 24
+---+---+---+---------+---+---------------+---------+
|///| | | |///| |/////////|
|///| P |NS | APF |///| Segment Limit |/////////|
|///| | | |///| |/////////|
+---+---+---+-+-------+---+---------------+-+---+---+
| | | | |///| |
| A | I | USE | Real Address |///| F |
| | | | |///| |
+---+---+-----+-----------------------------+---+---+
32 33 34 35 36 60 63
P - Segment Non-paged/Paged.
If the segment is paged, the real address, treated as a
double word aligned quantity (i.e. bits 36 - 60 are
used), points to the base of a page table. Otherwise the
real address points to the base of the segment which is
128 byte aligned (i.e. bits 57 - 60 are ignored).
NS - Segment Non-slaved/Slaved.
If NS = 0 (segment non-slaved), slave stores cannot be
used for items in this segment.
APF - Access Protection Field.
The ACF contains a read ACR, a write ACR and an
execute permission bit. These define the permissible
modes of access to the segment.
Segment Limit -
All references to the segment are checked to be less than
or equal to this value. When the segment is non-paged,
the segment limit is 128 byte aligned. Therefore a
segment can be any multiple of 128 bytes up to a limit of
256K bytes. If the segment is paged, in order to cater
for 1024 byte pages, bits 22 - 24 of the segment limit
should be set to 111, or undefined end effects may occur.
A - Segment Not Available/Available.
If A = 0 (i.e. segment not available) then a virtual
store interrupt occurs.
I - Segment Non-shared/Shared.
If the segment is shared, the real address points to a
Global Segment Table entry, double word aligned. If
this entry is shared, the indirection process is continued
until a non-shared entry is found (up to a maximum of 4
levels).
USE - Use Bits.
These bits indicate whether the segment has been written
to or read from.
F - Non-fixed/Fixed.
If the segment is fixed, it is locked down in store.
This is used as an indicator to peripheral controllers
that the segment can be used for I/O.
2.4 Page Tables.
0 2 3 4 21 31
+---+---+-----+----------------------+----------+---+
| |///| | |//////////| |
| A |///| USE | Real Address |//////////| F |
| |///| | |//////////| |
+---+---+-----+----------------------+----------+---+
The A, use and F sections of the page table have the
same functions as the corresponding sections in a segment table
entry. Pages are 1024 bytes long, so the real address is
always 1024 byte aligned.
3. The Image Store.
The image store is a uniform method of accessing all addressable
hardware registers in the system, whether the registers are internal
to the OCP or in some device controller, for example.
Image store locations are accessed using the image store
addressing mode of the LSS, LB, STB, CPB, L and ST
instructions. Privilege, which is needed to use this mode, is
governed by PRIV in PSR and DGR and ISR in SSR (see [2] p28).
The image store is notionally split into 2 sections: internal
and external registers.
3.1 Registers internal to the OCP.
The OCP registers themselves are split into 2 categories:
those which are accessible without privilege through normal
non-privileged instructions and addressing modes - the visible
registers - and those that are accessed with the privilege
which defines the virtual machine environment.
3.1.1 Visible Registers.
The visible registers are:
PC program counter
SF stack front
LNB local name base
XNB extra name base
SSN stack segment number
ACC accumulator
B index register
DR descriptor register
ACS* accumulator size
OV* overflow
CC* condition code
PM* program mask
RTC real time clock
* - visible portion of PSR below.
3.1.2 Invisible Registers.
The invisible registers are:
SSR system status register
PSR program status register
LSTB local segment table base
PSTB public segment table base
IT interval timer
IC instruction counter
RTZC periodic interrupt control
The system status register contains:
i) An interrupt mask (for system interrupts)
ii) A processor identifier
iii) Image store read/write permissions
iv) A real address mode indicator
The program status register contains:
i) The ACR
ii) The privileged bit (PRIV)
iii) D bit (see descriptors)
iv) OV, cc, PM, acs as above.
Note that PM, acs and CC can be altered by use of
the modify PSR instruction.
The invisible OCP registers cannot be written to
unless by image store addressing mode, i.e. a
non-privileged user cannot change the process environment.
3.2 External registers.
The external registers consist of SMAC, SAC, Trunk
registers, etc. I/O is controlled by writing to and reading
from SAC and peripheral controller registers through the image
store addressing mode. One major consequence of this is that
explicit I/O instructions are eliminated (in a similar but
more general manner to the PDP11).
4. New Range Order Code.
Instructions are either 16 or 32 bits and there are three
formats: primary, secondary and tertiary. Tertiary format is used
exclusively for jumps, secondary format is used for store to store
operations, i.e. string manipulation, and primary format is used
for the rest. In all formats the first 7 (i.e. most significant)
bits specify the function and this in turn decides the format. For
example, any function with the most significant 4 bits equal to zero
is a tertiary format instruction. The operand field, which
determines the instruction length, is decoded seperately for each
format. That is, the function determines the format and this
specifies how the operand field is decoded.
This means that, in general, a function can have any of the
types of operand associated with the format class to which it
belongs. In some cases, however, there will be a restriction on the
type of operand allowed. For example, in the Store DR
instruction, it makes no sense to specify the destination as being
indirect through a descriptor since DR would have to be loaded with
this descriptor in the process. Additionally, some instructions do
not use the operand (e.g. the EXIT instruction) and in these cases
a literal operand of zero must be specified.
4.1 The Stack.
The order code is oriented to the use of a hardware stack.
The stack is defined by 3 registers:
+---+
SSN -> | |
| |
| |
+---+
LNB -> | |
+---+
| |
| |
| |
+---+
|TOS| TOS - Top of stack item
+---+
SF -> | |
4.1.1 Stack Front (SF).
This register points to the next available word on the
stack. Whenever the destination of a store operation is
specified as tos (top of stack) the item is deposited at
sf and sf is incremented by the appropriate number of
locations. That is, if the accumulator is currently 64
bits and its contents are stacked, the value will be
stored at the words (sf) and (sf+1) and sf will be
incremented by 2. The inverse is true of load operations.
Note that sf cannot be loaded; it can only be stored and
adjusted. Adjustments of sf and displacements relative to
sf are by a number of words; when stored the value is a
byte address.
4.1.2 Local Name Base (LNB).
This register is used to define the start of the local
name space of a procedure. It can be raised relative to
the sf, loaded and stored. The hardware checks that lnb
is always less than sf.
4.1.3 Stack Segment Number (SSN).
The stack must only use one segment, identified by
ssn, and cannot overflow into the next segment even if the
last byte of the stack segment and the first byte of the
succeeding segment have contiguous addresses. That is,
the maximum size of the stack is 256k bytes.
4.2 Other User Addressable Registers.
4.2.1 Extra Name Base (XNB).
The lnb is used to access the local variables of a
procedure. The Extra Name Base (xnb) is provided to
access global variables or data in another segment. In a
high level language system, the lnb and xnb would normally
point to the current textual level and one other. So
overheads will occur if accesses are made outside these
areas. Note also that xnb cannot be stored. Therefore,
since a called environment cannot preserve the contents of
xnb, on return from a procedure which may have altered
xnb, you must assume that it has been corrupted and hence
must be reloaded.
4.2.2 Accumulator (ACC).
The accumulator register is 128 bits in length. It is
split into 4 by 32 bit sections, referred to as a0 (most
significant), a1, a2 and a3. The visible portion of the
accumulator is variable and is a3, a2 - a3, a0 - a3
depending on whether the register acs (accumulator size)
is 1, 2 or 3 (i.e. indicating 32, 64 or 128 bit length).
When acs is increased or decreased using Modify psr
it is extended on the left with zeroes or truncated on the
left respectively. The extended part is undefined if the
size is increased by writing direct to the image store
acs.
The accumulator size generally governs the length of
primary format operands. The operand length may not be
the same as the length of the addressed item in store. If
the lengths are different the rules are, in general:
a) The operand length should not be less
than the length of the addressed item.
b) If the operation is a load and the operand
length is greater than the length of the
addressed item, then the addressed item is
padded on the left with zeroes to the
appropriate length. The inverse applies to
store operations.
There are at least two cases where the second rule may
cause difficulties:
a) Evaluation of an integer expression with
mixed length operands. There is no sign
extension on the shorter quantities so
you must do this by program.
b) Evaluation of expressions involving mixed
real/long real operands. In this case you
want operands right extended with zeroes.
4.2.3 B Register.
The B register is a 32 bit index register. It is
used, primarily, for modifying descriptor addresses but
quite extensive arithmetic operations can be performed on
it and it can be used in loop control and the calculation
of array element addresses.
4.2.4 The Descriptor Register (DR).
The descriptor register holds a descriptor in standard
descriptor format or the result of an explicit dr
operation. Any indirect access (i.e. via a descriptor)
causes the descriptor used to be placed in the dr.
4.2.5 Overflow (OV).
This register is set when acc or B overflows. It can
be accessed by the Jump on Arithmetic Condition
instructions.
4.2.6 The Condition Code (CC).
The condition code is set by various instructions and
can be accessed by jump on condition instructions.
4.2.7 Program Mask (PM).
The program mask is used to inhibit or allow
interrupts produced by exceptional conditions within a
normal user program, e.g. overflow, array bound fault.
If the mask bit corresponding to a defined interrupt (see
[2] p22) is a 1 then the interrupt will be reset if it
occurs and execution will continue as if nothing had
happened.
4.2.8 The Real Time Clock (RTC).
The Read Real Time Clock instruction causes the
rtc, consisting of 2 by 32 bit registers, X and y, to be
read into bits 0 - 31 and 32 - 64 of the acc. X is
updated by system software but Y is a hardware binary
counter with a resolution of 2 microseconds at its least
significant bit.
4.3 Descriptors.
A descriptor is a 64 bit quantity which formally describes
an item of information in store. The addressing modes use
descriptors in several ways, described below.
The first word of the descriptor specifies the type of
information being addressed, the size of the item, the number
of units it contains, etc. The second word is the base address
of the item.
The general form of a descriptor is:
2 3 1 1 1 24
+------+------+---+-----+-----+----------------+
| | | | | | |
| type | size | A | usc | bci | Bound / Length | Word 1
| | | | | | |
+------+------+---+-----+-----+----------------+
| |
| B Y T E A D D R E S S | Word 2
| |
+----------------------------------------------+
A - Ignored. Must be zero.
usc - Unscaled.
bci - Bound Check Inhibit.
4.3.1 Vector Descriptors (type 0).
Vector descriptors address items of length 1, 8, 32,
64 or 128 bits, specified by the size field (0, 3, 5, 6 or
7, respectively). Note that 32, 64 and 128 bit quantities
are constrained to start on word boundaries. This is
ensured automatically by ignoring the least significant 2
bits of the byte address of the item being accessed. The
usc field is used to specify whether an applied modifier
is to be scaled according as the size field (i.e. >>3 for
1 bit, <<2 for 32 bit, <<3 for 64 bit and <<4 for 128 bit
quantities). The bci bit specifies whether an applied
modifier is to be checked (before scaling) against the
bound field (an unsigned 24 bit quantity).
4.3.2 String Descriptors (type 1).
The size field should be set to 3 (i.e. size 8 bits
as for type 0). usc and bci should be set to zero, since
modifications are neither checked nor scaled. The Length
field contains the length in bytes of the string. Word 2
of the descriptor addresses the first byte of the string.
4.3.3 Descriptor Descriptors (type 2).
These descriptors can be used interchangeably with
type 0 descriptors of size 64 bits. size should be set to
6 (i.e. size 64 bits as for type 0 descriptors).
4.3.4 Miscellaneous Descriptors (type 3).
Bits 2 - 7 specify a subtype number. The following
subtypes are range defined. Note, however, that there are
other implementation defined descriptors to describe, for
example, microprogram overlays.
4.3.4.1 Code Descriptors (subtype 32 or 34).
These descriptors may only be used to point to
the destinations of call and exit instructions. Word
2 contains the byte address of this instruction, word
aligned (least significant 2 bits ignored). When the
subtype is 32 - the bounded case - an applied
modifier is checked against the bound field as for
type 0 descriptors. In both cases, bounded and
unbounded, the modifier is left shifted one before
addition since the value of the modifier is taken to
be a number of half-words.
4.3.4.2 System Call Descriptors (subtype 35).
Again, these descriptors can only be used as the
destinations of call and exit instructions. System
call descriptors are used to make calls to more
privileged software in a similar fashion to the svc
mechanism.
4.3.4.3 Escape Descriptors (subtype 37).
This type of descriptor exists primarily to
implement thunks. If such a descriptor is loaded
into the dr by normal indirect action or one is found
in dr when the Modify dr instruction is used, the
following action is taken. The pc is stacked as a 32
bit quantity and a branch is made to a routine whose
32 bit address is specified by the contents of the
location pointed to by word 2 of the descriptor (a
byte address, word aligned). The esex (escape exit)
instruction is used at the end of such a routine,
loading the pc from the stack and setting the D bit
in psr. When this bit is set and indirection is
specified in an instruction, the indirection is
ignored and the descriptor already in dr is used, the
instruction then being executed and at the end the D
bit reset. Therefore the escape routine should load
into the dr the required descriptor and repeat the
interrupted instruction with this value.
4.4 Addressing Modes.
The notation used below is:
tos - top of stack item
Desc+mod - item addressed by descriptor at desc
modified by mod (except for Dr in which
case the descriptor is already in dr).
(expr) - item addressed by expr.
reg - can be replaced by lnb, xnb, pc, ssn.
4.4.1 Primary Addressing Modes.
Primary addressing modes use the operand field to
specify either a literal value or an address.
16 bit instructions can have the following operands:
n - signed 7 bit literal
(LNB+n) - n unsigned
(LNB+n) - n unsigned
tos - top of stack item
Tos - descriptor at the top of stack
Tos+b - " " " " " " modified by b.
Dr - descriptor in dr
Dr+b - " " " modified by B
Dr+tos - " " " modified by tos
B - B register
32 bit instructions can have the following operands:
N - 18 bit signed literal
(reg+n) - direct
(reg+n) - descriptor in store
(reg+n)+b - " " " modified
Dr+(reg+n) - " " dr "
Dr+n
is(n) - image store location N
is(b) - image store location B
Note that N is only signed when it is a literal or it is
added to the pc.
4.4.2 Secondary Addressing Modes.
Secondary instructions are the store to store
operations. Operands are specified by string or byte
descriptors in the dr (destination string) and/or the acc
(source string).
The operand field is decoded as follows:
+----------+---+---+----------+
| | | | |
| Function | H | Q | n |
| | | | |
+----------+---+---+----------+
7 1 1 7
If H = 0 then L = n + 1
else L = length of destination string,
where L is the number of bytes involved in the operation.
If Q = 0 then 16 bit instruction
else 32 bit instruction.
If the instruction is 32 bits then the second 16 bits
are interpreted as follows:
+----------------+----------------+
| | |
| mask | Literal/Filler |
| | |
+----------------+----------------+
8 8
If an instruction uses these fields and a 16 bit
format is specified, the mask is taken from bits 16 - 23
of the B register and the literal/filler from bits 24 -
31.
4.4.3 Tertiary Addressing Modes.
Tertiary instructions are the jump on condition
functions. Therefore the instruction provides a 4 bit
mask for condition testing and an operand. The operand
forms available are:
32 bit:
N
Dr+n
(reg+n)
16 bit:
Dr
Dr+b
4.5 Instructions.
The instructions of the machine can be broken up into the 8
sections below.
4.5.1 Stack Control Instructions.
These are the instructions which access registers sf,
lnb and xnb. Note the inconsistency between treatment of
registers:
load | store | adjust
| |
lnb | lnb | lnb
x | sf | sf
xnb | x | x
4.5.2 DR Instructions.
These instructions provide facilities for loading,
creating, modifying and checking descriptors in dr.
4.5.3 B Instructions.
Functions for loading, storing, comparing, comparing &
incrementing are provided as well as add, subtract,
multiply and a dope vector multiply to help calculation of
array element addresses.
4.5.4 Control Transfer Instructions.
The usual jump and jump on condition instructions are
provided. There is a cycle control instruction -
decrement B and jump if non-zero.
Three types of procedure call are implemented:
a) Jump and Link.
Same name space.
b) call.
Different name space.
c) Escape routines.
Binding procedure with the same name space (see above).
The call instruction is used in entering high level
language procedures. A link descriptor is placed at
(lnb+1) and (lnb+2) and the jump to the routine made.
This makes things awkward because it virtually enforces
the following entry sequence to be made by the calling
environment:
tos=lnb / store old lnb
sf=sf+2 / leave space for link
tos=parm1 / stack parameters
TOS=PARMn / n parameters
lnb=sf-parmsize-3 / lnb to link slots
call proc / enter
This means that responsibility for updating the stack
is left with the calling environment rather than with the
called environment, which would be more desirable.
Exits are provided for return from normal routines
(which return the stack to its status quo) and from escape
routines (see descriptors, above).
4.5.5 ACC Instructions.
acc can be stored, loaded, stacked & loaded and set to
a particular size before being loaded. Instructions are
provided to load and store the upper half of the
accumulator respectively doubling and halving the acc size
before and after the operation. This is useful for, say,
storing a long real into a real, i.e. you want the most
significant bits.
4.5.6 Computational Instructions.
There are a number of operations provided to convert
between the various data formats below. Reverse
operations are provided for non-commutative functions.
4.5.6.1 Logical Operations.
Logical functions on 128 bit quantities are not
allowed. Logical addition and subtraction cannot be
performed on items of 64 bits.
4.5.6.2 Decimal Operations.
Decimal operands are of the bcd format type.
Operations on up to 31 digits (plus sign) can be
performed (i.e. 31 * 4 bits + 4 bits for the sign =
128 bits).
4.5.6.3 Fixed Point Functions.
2's complement form is used for fixed point data.
Fixed point functions can be performed only on 32
and 64 bit items - not 128 bits, however.
4.5.6.4 Floating Point Functions.
The ibm 360/370 format is used for floating point
items of up to 128 bits in length.
4.5.7 String Instructions.
These are the tertiary format store to store
functions. They are performed between a string described
by a descriptor in dr and either:
a) a string described by a descriptor in acc.
(for move, and strings, etc)
b) a literal.
(for Move Literal, Scan While Equal, etc)
c) the accumulator direct.
(for converting from zoned decimal to
packed decimal and the reverse)
4.5.8 Sundries.
This heading covers the semaphore instructions (test and
decrement, increment and test), read real time clock,
diagnose, activate (a cpu), idle and out.
5. Interrupt Structure.
There are 12 classes of interrupt:
1. System Error.
Hardware errors and system software errors.
2. External.
From devices not having a direct connection with the
store. For example, real time clock, mains monitor.
3. Multiprocessor.
Interrupts between processors sharing the same store.
4. Peripheral.
Interrupts from peripheral controllers via sac.
5. Virtual Store.
Access to non-available segment/page or access outside
virtual memory.
6. Timer Interrupts.
7. Program Error.
2 type of program error interrupts:
a) Maskable, e.g. overflow.
b) Non-maskable, e.g. illegal instruction.
8. System Call.
Interrupt generated by system call descriptor used as
destination of a call or exit instruction.
9. Out.
Voluntary interrupt by software.
10. Extracode.
Means of implementing an assigned function by software.
11. Event Pending.
Used for synchronising processes working largely
independent of one an other.
12. Instruction counter.
The interrupt mask in ssr (see above) has a bit for each of the
interrupt classes.
The Interrupt Steering Table (ist) holds 12 areas, one for
each of the classes of interrupt, from which registers are loaded
when an interrupt occurs. The ist is held in segment 8192, i.e.
the first public segment. Each entry is eight words long
containing:
ssn/lnb
psr *
pc *
ssr
sss/sf
it
ic.
* - These are the only entries accessed if the stack is not
switched.
The 12 interrupt classes above are split into 2 categories:
1) Stack Switching Interrupts.
2) Non-stack Switching Interrupts.
Themselves split into 2 sections:
a) System call (class 8)
b) Extracode and instruction counter (classes 10, 12).
The procedures taken for these different types of interrupts are
as follows.
Get the interrupt type (stack switching, non-stack switching,
system call).
Get the interrupt class (1 -> 12 above) in order to indentify
the appropriate ist entry.
System Call.
Load new psr without overwriting acs.
Load new pc.
Non-stack Switching.
Unless 7 words at tos, v.m. interrupt.
tos=ssn/lnb
Stack pc as a code descriptor with psr as bits 8-31 of
the first word of the descriptor.
sf=sf+2
TOS=interrupt parameter
lnb=sf-6
Load pc, psr without overwriting acs.
Stack Switching.
Dump all user accessible registers and psr, ssr, it, ic
in words 0 to 15 of segment ssn+1. (there mat be some
extra, implementation defined, information dumped from
words 16 onwards if a long instruction has been
interrupted in mid flight).
Load the new registers from ist.
Stack the interrupt parameter.
If this is a program error, then store the address of the
offending instruction in word 16 of the old ssn+1.
Stack the old ssn.
The interrupt parameter supplies the software with extra
information about the interrupt. For example, in the case of the
program error interrupt, the parameter would identify the cause of
the program error, e.g. whether it was an illegal instruction or a
bound check.